Patrick Georgi submitted this change.
soc/qualcomm/sc7180: Adapt to recent API changes
Definitions were moved so that now device/mmio.h needs to be included
instead of arch/mmio.h. Also, don't use le32 conversion.
This follows the activities of commit 55009af42 (Change all
clrsetbits_leXX() to clrsetbitsXX()) and commit 1c371572188 (mmio: Add
clrsetbitsXX() API in place of updateX()).
Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37534
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7180/usb.c
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c
index 97b7b28..9092a4e 100644
--- a/src/soc/qualcomm/sc7180/clock.c
+++ b/src/soc/qualcomm/sc7180/clock.c
@@ -62,10 +62,10 @@
static int clock_configure_gpll0(void)
{
- setbits_le32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT);
+ setbits32(&gcc->gpll0.user_ctl_u, 1 << SCALE_FREQ_SHFT);
/* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */
- setbits_le32(&gcc->gpll0.user_ctl,
+ setbits32(&gcc->gpll0.user_ctl,
1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT |
1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT |
1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT);
@@ -77,7 +77,7 @@
uint32_t d_2)
{
struct sc7180_mnd_clock *mnd = (struct sc7180_mnd_clock *)clk;
- setbits_le32(&clk->rcg_cfg,
+ setbits32(&clk->rcg_cfg,
RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK);
@@ -111,7 +111,7 @@
clk_cfg[idx].d_2);
/* Commit config to RCG*/
- setbits_le32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+ setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
return 0;
}
@@ -125,7 +125,7 @@
uint32_t vote_bit)
{
/* Set clock vote bit */
- setbits_le32(vote_addr, BIT(vote_bit));
+ setbits32(vote_addr, BIT(vote_bit));
/* Ensure clock is enabled */
while (clock_is_off(cbcr_addr))
@@ -137,7 +137,7 @@
static int clock_enable(void *cbcr_addr)
{
/* Set clock enable bit */
- setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+ setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
/* Ensure clock is enabled */
while (clock_is_off(cbcr_addr))
@@ -149,7 +149,7 @@
void clock_reset_aop(void)
{
/* Bring AOP out of RESET */
- clrbits_le32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT));
+ clrbits32(&aoss->aoss_cc_apcs_misc, BIT(AOP_RESET_SHFT));
}
void clock_configure_qspi(uint32_t hz)
@@ -166,9 +166,9 @@
struct sc7180_bcr *bcr = bcr_addr;
if (reset)
- setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+ setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
else
- clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+ clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
return 0;
}
diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c
index 4183e9b..639f401 100644
--- a/src/soc/qualcomm/sc7180/usb.c
+++ b/src/soc/qualcomm/sc7180/usb.c
@@ -13,10 +13,10 @@
* GNU General Public License for more details.
*/
-#include <arch/mmio.h>
#include <stdlib.h>
#include <console/console.h>
#include <delay.h>
+#include <device/mmio.h>
#include <soc/usb.h>
#include <soc/clock.h>
#include <soc/addressmap.h>
@@ -565,7 +565,7 @@
* tune parameters.
*/
if (tune_val)
- clrsetbits_le32(&dwc3->qusb_phy_dig->tune1,
+ clrsetbits32(&dwc3->qusb_phy_dig->tune1,
PORT_TUNE1_MASK, tune_val << 4);
}
@@ -602,7 +602,7 @@
static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3)
{
/* PWR_CTRL: set the power down bit to disable the PHY */
- setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
+ setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
write32(&dwc3->qusb_phy_pll->analog_controls_two,
QUSB2PHY_PLL_ANALOG_CONTROLS_TWO);
@@ -622,7 +622,7 @@
tune_phy(dwc3, dwc3->qusb_phy_dig);
/* PWR_CTRL1: Clear the power down bit to enable the PHY */
- clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
+ clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
write32(&dwc3->qusb_phy_dig->debug_ctrl2,
DEBUG_CTRL2_MUX_PLL_LOCK_STATUS);
@@ -688,7 +688,7 @@
static void setup_dwc3(struct usb_dwc3 *dwc3)
{
/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
- clrsetbits_le32(&dwc3->usb3pipectl,
+ clrsetbits32(&dwc3->usb3pipectl,
DWC3_GUSB3PIPECTL_DELAYP1TRANS,
DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
@@ -698,18 +698,18 @@
* 2. Set USBTRDTIM to the corresponding value
* according to the UTMI+ PHY interface.
*/
- clrsetbits_le32(&dwc3->usb2phycfg,
+ clrsetbits32(&dwc3->usb2phycfg,
(DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
DWC3_GUSB2PHYCFG_PHYIF_MASK),
(DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT)));
- clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
+ clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
DWC3_GCTL_DISSCRAMBLE),
DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
/* configure controller in Host mode */
- clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+ clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
printk(BIOS_SPEW, "Configure USB in Host mode\n");
}
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