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1 comment:
Patchset:
Patch Set #16:
AIUI, at least all the Intel devices use (virtual) PCI INT lines + PIRQ. […]
13.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
By "PCI device with IOAPIC MMIO" I mean the PCI device that decodes MMIO at 0xfec00000 and is the PCI initiator for interrupt messages. LPC on Intel, SMBUS on AMD, AFAIR.
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