Patch Set 5:

Patch Set 5:

Patch Set 5:

Why was this merged? Furquan has a point.

oops, i thought Furquan said, lets not replicate this for Google ADL boards where partners need more configurability

Alright. I think we can wait until some Google ADL boards are in the tree, then restructure memcfg to better reflect LPDDR byte mapping logic.

Yes, let's do that. I think it is important to keep the translation from schematics to mainboard description as simple and straightfoward as possible. The complexities can be hidden inside SoC code to translate into appropriate UPDs, etc. This makes life easier for mainboard developers.

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1 comment:

• File src/mainboard/intel/adlrvp/memory.c:

  • Patch Set #4, Line 25: { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 },

    For volteer, how about using a struct instead? This would allow each group of 8 numbers to be labell […]

    Yeah, that would make sense. We will have to go back and clean things up as new boards get added.

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