Attention is currently required from: Angel Pons, Evgeny Zinoviev.
2 comments:
Commit Message:
Patch Set #5, Line 9: Do not consider the failed channel's SPDs in emergency mode. Also, force
In very weird corner cases, this may fail while it worked before.
For instance, two broken DIMMs and the faster rated one happened
to work only with the SPD data of the slower. As I understand this
change, the originally succeeding DIMM would then be trained again
with only its own SPD data and may fail now even though it worked
with the combined data.
Just wanted to mention that because the commit message currently
suggests (to me) that this change could only yield better results.
File src/northbridge/intel/sandybridge/raminit.c:
I would much prefer to not write to the cache in emergency mode
in the first place. Worst case scenario: training of one channel
succeeds marginally, but DRAM doesn't work reliably and the system
resets during boot. We'd write to flash in a loop. I guess the flash
could survive that for a year in that loop or so, but it seems much
better to avoid it.
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