Tristan Corrick has uploaded this change for review.

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sb/intel/lynxpoint: Provide a function for mainboard super I/O config

The super I/O setup needs to be done after the LPC is enabled. For
Lynx Point, configuring the super I/O in `mainboard_romstage_entry()`
is too early to get a serial console output. To remedy this, add a
function `mainboard_config_superio()` that will be called at the
appropriate time, and can be overridden by mainboard code.

Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
---
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/pch.h
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29382/1

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 8e11f10..27a3b29 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -124,6 +124,10 @@
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
+void __weak mainboard_config_superio(void)
+{
+}
+
 int early_pch_init(const void *gpio_map,
 		   const struct rcba_config_instruction *rcba_config)
 {
@@ -139,6 +143,8 @@
 	setup_pch_gpios(gpio_map);
 #endif
 
+	mainboard_config_superio();
+
 	console_init();
 
 	pch_generic_setup();
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 489b565..1e59479 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -206,6 +206,7 @@
 int early_pch_init(const void *gpio_map,
                    const struct rcba_config_instruction *rcba_config);
 void pch_enable_lpc(void);
+void mainboard_config_superio(void);
 #endif /* !__PRE_RAM__ && !__SMM__ */
 #endif /* __ASSEMBLER__ */
 

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