[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31284 )

Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML
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Patch Set 11:

(1 comment)

https://review.coreboot.org/#/c/31284/10/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/31284/10/src/soc/intel/cannonlake/chip.h@295 
PS10, Line 295: #if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE)
              : 	/*
              : 	 * SerialIO device mode selection:
              : 	 * PchSerialIoDisabled,
              : 	 * PchSerialIoPci,
              : 	 * PchSerialIoHidden,
              : 	 * PchSerialIoLegacyUart,
              : 	 * PchSerialIoSkipInit
              : 	 */
              : 	uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
              : 	uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
              : 	uint8_t SerialIoUartMode[SOC_INTEL_CML_UART_DEV_MAX];
              : #else
> we can do that i believe so that we can use old config structure as below.

Done