Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph.
2 comments:
File src/soc/intel/alderlake/fsp_params.c:
Patch Set #7, Line 210: int i;
nit: `size_t` and this can just go in the loop below: […]
Ack
static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* PCH UART selection for FSP Debug */
s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
}
static void fill_fsps_sata_port_power_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
int i;
/*
* Power Optimizer for SATA.
* SataPwrOptimizeDisable is default to 0.
* Boards not needing the optimizers explicitly disables them by setting
* these disable variables to 1 in devicetree overrides.
*/
s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
/*
* Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
* SataPortsDmVal is the DITO multiplier. Default is 15.
* SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
* The default values can be changed from devicetree.
*/
for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
if (config->SataPortsEnableDitoConfig[i]) {
s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i];
s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
}
}
}
IMHO, these could just go in the fsps_sata_params function below
Ack
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