[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/xeon_sp: Redesign resource allocation

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )

Change subject: soc/intel/xeon_sp: Redesign resource allocation
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Patch Set 4:

(5 comments)

File src/device/pci_device.c:

https://review.coreboot.org/c/coreboot/+/78327/comment/dd8d0d56_00b3159c :
PS4, Line 591: static void host_bridge_resources(struct device *dev)
Nit, the other function names around are much more verbose, e.g. this
could be `pci_host_bridge_read_resources()`.

https://review.coreboot.org/c/coreboot/+/78327/comment/0d9f10aa_d5609028 :
PS4, Line 617: uint16_t
For PCI this is always limited to 255, i.e. `uint8_t`, isn't it? I'm actually
not sure about PCIe extensions...

Also, shouldn't we set the `max_subordinate` here, i.e. where the bus window for
this host bridge ends? Does the caller know it?

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/78327/comment/60d78db3_19871714 :
PS4, Line 17: 	const IIO_UDS *hob = get_iio_uds();
Could be NULL

https://review.coreboot.org/c/coreboot/+/78327/comment/cfce9eec_abb862dc :
PS4, Line 18: MAX_IIO_STACK
Here comes the fun: SKX uses MAX_IIO_STACK to size this, but CPX on use
MAX_LOGIC_IIO_STACK. I'm not sure what is the right thing to do here.
The current effect seems to be that we skip 2 stack entries from the HOB
per node. Is this intended?

If we change this, the setting `path.domain.domain` below needs to be
adjusted as well.

https://review.coreboot.org/c/coreboot/+/78327/comment/04d4a93f_31e4b15c :
PS4, Line 99: 		host_bridge->link_list->max_subordinate = i;
Could me make this an additional parameter to alloc_pci_host_bridge()?