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Documentation/soc/amd: Add family 15h

Create documentation for AMD family 15h, and in particular to models for
which there's coreboot code: Models 60h-6Fh and 70h-7Fh.

BUG=none.
TEST=none.

Change-Id: Iaab4edc431329a691283121494595f3797c566c6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
A Documentation/soc/amd/family15h.md
M Documentation/soc/amd/index.md
2 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34561/1

diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md
new file mode 100644
index 0000000..2e583e8
--- /dev/null
+++ b/Documentation/soc/amd/family15h.md
@@ -0,0 +1,44 @@
+# AMD Family 15h in coreboot
+
+## Abstract
+
+Family 15h uses the AMD CPU micro architecture _Excavator_, and is available
+in several models with different number of cores and some other small
+variations, to attend a broad spectrum of users. Of particular interest for
+coreboot are models **60h-6Fh** (_Merlin Falcon_) and **70h-7Fh** (_Stoney Ridge_),
+for which there are coreboot implementations.
+
+## Introduction
+
+Family 15h products are x86-based designs.  This documentation assumes
+familiarity with x86, its reset state and its early initialization requirements.
+
+AMD has historically required an NDA for access to the PSP specification.
+coreboot relies on util/amdfwtool to build the structures and add various
+other firmware to the final image.
+
+Support in coreboot for modern AMD products is based on AMD’s
+reference code:  AMD Generic Encapsulated Software Architecture
+(AGESA _**TM**_).  AGESA contains the technology for enabling DRAM,
+configuring proprietary core logic, assistance with generating ACPI
+tables, and other features.
+
+Some functionality, such as GPIO setting and D0/D3 of some devices such as
+I2C and UART were removed from AGESA (though still available on most AGESA
+images) and converted to coreboot code for granularity, speed and easy of
+use reasons.
+>In particular, GPIO achieved a greater control over what is being
+>programmed through the use of a table that is easily created using
+>macros.
+
+## Additional Definitions
+
+*   PSP, Platform Security Processor:  Onboard ARM processor that runs
+alongside the main x86 processor; may be viewed as analogous to the
+Intel<sup>R</sup> Management Engine
+*   FCH, Fusion Control Hub, the logical southbridge within the SOC
+
+## References
+
+1. [Merlin Falcon BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf)
+2. [Stoney Ridge BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf)
diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md
index 7945b48..d6f31c8 100644
--- a/Documentation/soc/amd/index.md
+++ b/Documentation/soc/amd/index.md
@@ -4,5 +4,6 @@
 
 ## Technology
 
+- [Family 15h](family15h.md)
 - [Family 17h](family17h.md)
 

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