Attention is currently required from: Philipp Hug, ron minnich.

Elyes Haouas has uploaded this change for review.

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arch/riscv: Fix build with binutils 2.38

The fix is to specify 'zicsr' 'zifencei' extensions explicitely in
-march.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Iac002a9eab58313f6ecce77a98371c1ad8bf2fe2
---
M src/arch/riscv/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62491/1
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 272768d..d8f73ea 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -22,7 +22,7 @@
endif

ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
-riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
+riscv_flags += -march=$(CONFIG_RISCV_ARCH)_zicsr_zifencei -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
else
riscv_flags += $(_rv_flags)
endif

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iac002a9eab58313f6ecce77a98371c1ad8bf2fe2
Gerrit-Change-Number: 62491
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes Haouas <ehaouas@noos.fr>
Gerrit-Reviewer: Philipp Hug <philipp@hug.cx>
Gerrit-Reviewer: ron minnich <rminnich@gmail.com>
Gerrit-Attention: Philipp Hug <philipp@hug.cx>
Gerrit-Attention: ron minnich <rminnich@gmail.com>
Gerrit-MessageType: newchange