Sugnan Prabhu S would like Aamir Bohra to review this change.
mb/intel/sm: Update the GPIO configuration
Change-Id: I2f34232371f6062a0a61b7619d318c127845bc8f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
1 file changed, 223 insertions(+), 218 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48457/1
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
index e63416c..47d4984 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
@@ -7,40 +7,42 @@
/* Pad configuration in ramstage */
/* Leave eSPI pins untouched from default settings */
static const struct pad_config gpio_table[] = {
- /* A0-A4 A9-A10 come configured out of reset, do not touch */
+ /* A0 thru A6 come configured out of reset, do not touch */
/* A0 : ESPI_IO0 ==> ESPI_IO_0 */
/* A1 : ESPI_IO1 ==> ESPI_IO_1 */
/* A2 : ESPI_IO2 ==> ESPI_IO_2 */
/* A3 : ESPI_IO3 ==> ESPI_IO_3 */
/* A4 : ESPI_CS# ==> ESPI_CS_L */
/* A9 : ESPI_CLK ==> ESPI_CLK */
- /* A10 : ESPI_RESET# ==> NC(TP764) */
+ /* A10 : ESPI_RESET ==> ESPI_RESET */
/* A5 : USB_C0_AUXP_DC */
- PAD_NC(GPP_A5, NONE),
+ PAD_CFG_GPO(GPP_A5, 1, DEEP),
/* A6 : USB_C0_AUXN_DC */
- PAD_NC(GPP_A6, NONE),
- /* A8 : EC_IN_RW_OD */
+ PAD_CFG_GPO(GPP_A6, 1, DEEP),
+ /* A8 : EC_IN_RW_OD */
PAD_CFG_GPI(GPP_A8, NONE, DEEP),
/* A11 : PMC_I2C_SDA ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
- /* A13 : BT_DISABLE_L */
- PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A13 : BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
/* A14 : USB_OC1# ==> USB_A0_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> USB_A1_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
- /* A16 : USB_C0_OC_ODL */
- PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
- /* A18 : HDMI_HPD */
- PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
- /* A21 : EN_FP_PWR */
- PAD_CFG_GPO(GPP_A21, 1, DEEP),
- /* A22 : EN_HDMI_PWR */
- PAD_CFG_GPO(GPP_A22, 1, DEEP),
- /* A23 : EN_SPKR_PA */
- PAD_CFG_GPO(GPP_A23, 1, DEEP),
+ /* A16 : USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* A18 : HDMI_HPD */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* A21 : EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : EN_HDMI_PWR */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A23, 1, DEEP),
/* B0 : CORE_VID0 */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
@@ -48,22 +50,18 @@
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> VRALERT_L */
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
- /* B3 : PEN_DET_ODL */
- PAD_NC(GPP_B3, NONE),
- /* B4 : WiFi_DISABLE_L */
+ /* B3 : PEN_DET_ODL */
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+ /* B4 : WiFi_DISABLE_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
- /* B5 : PCH_I2C2_1V8_AUDIO_SDA */
+ /* B5 : ISH_I2C0_CVF_SDA */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
- /* B6 : PCH_I2C2_1V8_AUDIO_SCL */
+ /* B6 : ISH_I2C0_CVF_SCL */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
- /* B7 : PCH_I2C3_TOUCH_USI_SDA */
+ /* B7 : ISH_I2C0_SENSOR_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
- /* B8 : PCH_I2C3_TOUCH_USI_SCL */
+ /* B8 : ISH_I2C0_SENSOR_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
- /* B9 : I2C5_SDA ==> NC */
- PAD_NC(GPP_B9, NONE),
- /* B10 : I2C5_SCL ==> NC */
- PAD_NC(GPP_B10, NONE),
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B12 : SLP_S0# ==> SLP_S0_L */
@@ -72,22 +70,16 @@
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B15 : FPMCU_INT_L */
- PAD_NC(GPP_B15, NONE),
+ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, LEVEL),
/* B16 : PCH_I2C5_TRACKPAD_SDA */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
/* B17 : PCH_I2C5_TRACKPAD_SCL */
- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
/* B18 : EN_PP5000_TRACKPAD */
PAD_CFG_GPO(GPP_B18, 1, DEEP),
- /* B19 : NC */
- PAD_NC(GPP_B19, NONE),
- /* B20 : NC */
- PAD_NC(GPP_B20, NONE),
- /* B21 : NC */
- PAD_NC(GPP_B21, NONE),
- /* B22 : NC */
- PAD_NC(GPP_B22, NONE),
/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
PAD_NC(GPP_B23, NONE),
@@ -105,82 +97,86 @@
PAD_NC(GPP_C5, NONE),
/* C6 : SML1CLK ==> EC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT),
- /* C7 : FPMCU_RST_ODL */
+ /* C7 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_C7, 1, DEEP),
- /* D0 : SSD_RTD3_EN */
- PAD_CFG_GPO(GPP_D0, 1, DEEP),
- /* D1 : ISH_GP1 ==> NC */
+ /* D0 : SSD_RTD3_EN */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP),
+ /* D1 : ISH_ACCEL_INT_L */
PAD_NC(GPP_D1, NONE),
- /* D2 : ISH_GP2 ==> NC */
+ /* D2 : ISH_LID_OPEN */
PAD_NC(GPP_D2, NONE),
- /* D3 : ISH_GP3 ==> NC */
+ /* D3 : ISH_ALS_RGB_INT_L */
PAD_NC(GPP_D3, NONE),
- /* D4 : FCAM_RST_L */
- PAD_CFG_GPO(GPP_D4, 0, PLTRST),
- /* D5 : SSD_CLKREQ_ODL */
- PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
- /* D6 : WLAN_CLKREQ_ODL */
- PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
- /* D8 : SD_CLKREQ_ODL */
- PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
- /* D9 : SD_PE_WAKE_ODL */
- PAD_CFG_GPI(GPP_D9, NONE, DEEP),
- /* D10 : EN_PP3300_WWAN */
- PAD_CFG_GPO(GPP_D10, 1, DEEP),
- /* D11 : PEN_ALERT_ODL */
- PAD_CFG_GPI(GPP_D11, NONE, DEEP),
- /* D12 : PCH_FPMCU_BOOT0 */
- PAD_CFG_GPO(GPP_D12, 0, DEEP),
- /* D13 : UART_ISH_RX_DEBUG_TX */
- PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
- /* D14 : UART_ISH_TX_DEBUG_RX */
- PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
- /* D16 : EN_PP3300_SD */
- PAD_CFG_GPO(GPP_D16, 1, DEEP),
- /* D17 : EN_FCAM_PWR */
- PAD_CFG_GPO(GPP_D17, 1, DEEP),
- /* D18 : EN_FCAM_SNR_PWR */
- PAD_CFG_GPO(GPP_D18, 1, DEEP),
+ /* D4 : FCAM_RST_L */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+ /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D7 : SRCCLKREQ2# ==> NC */
+ PAD_NC(GPP_D7, NONE),
+ /* D8 : SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D9 : SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+ /* D10 : EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ /* D11 : PEN_ALERT_ODL */
+ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+ /* D12 : PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_D12, 0, DEEP),
+ /* D13 : UART_ISH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* D14 : UART_ISH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+ /* D16 : EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 0, DEEP),
+ /* D18 : FCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_D18, 0, DEEP),
/* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
PAD_CFG_GPO(GPP_E0, 1, DEEP),
- /* E1 : PEN_DET_ODL */
- PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
- /* E2 : WLAN_PCIE_WAKE_ODL */
- PAD_CFG_GPI(GPP_E2, NONE, DEEP),
- /* E3 : USI_REPORT_EN */
- PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ /* E1 : PEN_DET_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+ /* E2 : WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 0, DEEP),
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
PAD_NC(GPP_E4, NONE),
/* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
PAD_NC(GPP_E6, NONE),
- /* E7 : USI_INT */
- PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
- /* E8 : SLP_S0IX */
- PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E7 : USI_INT */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+ /* E8 : SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
- /* E10 : PCH_GSPI0_H1_TPM_CS_L */
- PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
- /* E11 : PCH_GSPI0_H1_TPM_CLK */
- PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
- /* E12 : PCH_GSPIO_H1_TPM_MISO */
- PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
- /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
- PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
+ /* E10 : PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
+ /* E11 : PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
+ /* E12 : PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
+ /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
- /* E15 : WWAN_CONFIG0 */
- PAD_CFG_GPI(GPP_E15, NONE, DEEP),
- /* E16 : FPMCU_INT_L */
- PAD_CFG_GPI_INT(GPP_E16, NONE, PLTRST, LEVEL),
- /* E17 : WWAN_PERST_L */
- PAD_CFG_GPO(GPP_E17, 1, DEEP),
+ /* E15 : TRACKPAD_INT_ODL */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+ /* E16 : WWAN_SIM1_DET_OD */
+ PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+ /* E17 : WWAN_PERST_L */
+ PAD_CFG_GPO(GPP_E17, 1, DEEP),
/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
@@ -206,38 +202,38 @@
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
/* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
- /* F6 : WWAN_CONFIG3 */
- PAD_CFG_GPI(GPP_F6, NONE, DEEP),
- /* A7 : EN_PP3300_TRACKPAD */
- PAD_CFG_GPO(GPP_F7, 1, DEEP),
+ /* F6 : WWAN_CONFIG3 */
+ PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+ /* F7 : EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_F7, 1, DEEP),
/* F8 : I2S_MCLK2_INOUT ==> NC */
PAD_NC(GPP_F8, NONE),
- /* F9 : HP_INT_L */
- PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH),
- /* F10 : EN_PP3300_TOUCHSCREEN */
- PAD_CFG_GPO(GPP_F10, 0, DEEP),
- /* F11 : PCH_GSPI1_FPMCU_CLK */
- PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
- /* F12 : PCH_GSPI1_FPMCU_MISO */
- PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
- /* F13 : PCH_GSPI1_FPMCU_MISO */
- PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
- /* F14 : WLAN_RST_ODL */
- PAD_CFG_GPO(GPP_F14, 1, DEEP),
- /* F15 : RCAM_RST_L */
- PAD_CFG_GPO(GPP_F15, 1, DEEP),
- /* F16 : PCH_GSPI1_FPMCU_CS_L */
- PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
- /* F17 : WWAN_RF_DISABLE_ODL */
- PAD_CFG_GPO(GPP_F17, 1, DEEP),
- /* F18 : WWAN_PCIE_WAKE_ODL */
- PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
- /* F19 : WLAN_INT_L */
- PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
- /* F20 : WWAN_RST_ODL */
- PAD_CFG_GPO(GPP_F20, 1, DEEP),
- /* F21 : WWAN_DPR_SAR_ODL */
- PAD_CFG_GPO(GPP_F21, 1, DEEP),
+ /* F9 : HP_INT_L */
+ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH),
+ /* F10 : EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_F10, 0, DEEP),
+ /* F11 : PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+ /* F12 : PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+ /* F13 : PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+ /* F14 : WLAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F14, 1, DEEP),
+ /* F15 : RCAM_RST_L */
+ PAD_CFG_GPO(GPP_F15, 1, DEEP),
+ /* F16 : PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+ /* F17 : WWAN_RF_DISABLE_ODL */
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ /* F18 : WWAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+ /* F19 : WLAN_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+ /* F20 : WWAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F20, 1, DEEP),
+ /* F21 : WWAN_DPR_SAR_ODL */
+ PAD_CFG_GPO(GPP_F21, 1, DEEP),
/* F22 : VNN_CTRL */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* F23 : V1P05_CTRL */
@@ -249,80 +245,79 @@
PAD_NC(GPP_H1, NONE),
/* H2 : GPPH2_BOOT_STRAP3 */
PAD_NC(GPP_H2, NONE),
- /* H3 : SD_PERST_L */
- PAD_CFG_GPO(GPP_H3, 1, DEEP),
- /* H4 : PCH_I2C0_MISC_SDA */
+ /* H3 : SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H4 : PCH_I2C0_MISC_SCL */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
- /* H5 : PCH_I2C0_MISC_SCL */
+ /* H5 : PCH_I2C0_MISC_SDA */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
- /* H6 : I2C3_SDA ==> PCH_I2C3_MISC_SDA */
+ /* H6 : PCH_I2C1_CAM_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
- /* H7 : I2C3_SCL ==> PCH_I2C3_MISC_SCL */
+ /* H7 : PCH_I2C1_CAM_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
- /* H8 : WWAN_WLAN_COEX1 */
- PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
- /* H9 : WWAN_WLAN_COEX2 */
- PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
- /* H10 : UART_PCH_RX_DEBUG_TX */
- PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
- /* H11 : UART_PCH_RX_DEBUG_TX */
- PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
-/* H12 : WWAN_CONFIG0 */
- PAD_NC(GPP_H12, NONE),
-/* H13 : EN_RCAM_SNR_PWR */
- PAD_NC(GPP_H13, NONE),
- /* H14 : M2_SKT2_CFG2 # ==> NC */
- PAD_NC(GPP_H14, NONE),
- /* H15 : DDPB_HDMI_CTRLCLK */
- PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
- /* H17 : DDPB_HDMI_CTRLDATA */
- PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* H8 : WWAN_WLAN_COEX1 */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+ /* H9 : WWAN_WLAN_COEX2 */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+ /* H10 : UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART_PCH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+ /* H12 : WWAN_CONFIG0 */
+ PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+ /* H13 : RCAM_SNRPWR_EN */
+ PAD_CFG_GPO(GPP_H13, 0, DEEP),
+ /* H15 : DDPB_HDMI_CTRLCLK */
+ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+ /* H16 : DDPB_CTRLCLK ==> NC */
+ PAD_NC(GPP_H16, NONE),
+ /* H17 : DDPB_HDMI_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
-/* H19 : USB_C1_RT_FORCE_PWR */
- PAD_NC(GPP_H19, NONE),
- /* H20 : EN_MIPI_RCAM_PWR */
- PAD_CFG_GPO(GPP_H20, 0, DEEP),
- /* H21 : CAM_MCLK1 */
- PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
- /* H22 : CAM_MCLK0 */
- PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
-/* H23 : WWAN_ESIM_SEL_ODL */
+ /* H19 : USB_C1_RT_FORCE_PWR */
+ PAD_CFG_GPO(GPP_H19, 1, DEEP),
+ /* H20 : EN_MIPI_RCAM_PWR */
+ PAD_CFG_GPO(GPP_H20, 0, DEEP),
+ /* H21 : CAM_MCLK1 */
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ /* H22 : CAM_MCLK0 */
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+ /* H23 : IMGCLKOUT4 ==> NC */
PAD_NC(GPP_H23, NONE),
- /* R0 : I2S0_HP_SCLK */
- PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
- /* R1 : I2S0_HP_SFRM */
- PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
- /* R2 : I2S0_PCH_TX_HP_RX_STRAP */
- PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
- /* R3 : I2S0_PCH_RX_HP_TX */
- PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
- /* R4 : DMIC_CLK0 */
- PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
- /* R5 : DMIC_DATA0 */
- PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
-/* R6 : WWAN_WLAN_COEX3 */
- PAD_NC(GPP_R6, NONE),
-/* R7 : SAR0_INT_L */
- PAD_NC(GPP_R7, NONE),
+ /* R0 : I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R4 : DMIC_CLK0 */
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+ /* R5 : DMIC_DATA0 */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+ /* R6 : WWAN_WLAN_COEX3 */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
+ /* R7 : SAR0_INT_L */
+ PAD_CFG_GPI_APIC(GPP_R7, NONE, PLTRST, LEVEL, NONE),
-/* S0 : SNDW0_CLK ==> NC */
- PAD_NC(GPP_S0, NONE),
- /* S1 : SNDW0_DATA ==> NC */
- PAD_NC(GPP_S1, NONE),
- /* S2 : SNDW1_CLK ==> NC */
- PAD_NC(GPP_S2, NONE),
- /* S3 : SNDW1_DATA ==> NC */
- PAD_NC(GPP_S3, NONE),
- /* S4 : SNDW2_CLK ==> NC */
- PAD_NC(GPP_S4, NONE),
- /* S5 : SNDW2_DATA ==> NC */
- PAD_NC(GPP_S5, NONE),
- /* S6 : SNDW3_CLK ==> NC */
- PAD_NC(GPP_S6, NONE),
- /* S7 : SNDW3_DATA ==> NC */
- PAD_NC(GPP_S7, NONE),
+
+ /* S0 : I2S1_SPKR_SCLK */
+ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
+ /* S1 : I2S1_SPKR_SFRM */
+ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
+ /* S2 : I2S1_PCH_TX_SPKR_RX */
+ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
+ /* S3 : I2S1_PCH_TX_SPKR_RX */
+ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
+ /* S5 : SPKR_INT_L */
+ PAD_CFG_GPI_APIC(GPP_S5, NONE, PLTRST, LEVEL, NONE),
+ /* S6 : DMIC_CLK1 */
+ PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+ /* S7 : DMIC_DATA1 */
+ PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
/* GPD0: BATLOW# ==> BATLOW_L */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
@@ -342,50 +337,60 @@
PAD_CFG_GPI(GPD7, DN_20K, DEEP),
/* GPD8: SUSCLK ==> PCH_SUSCLK */
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
- /* GPD9: SLP_WLAN# ==> NC */
- PAD_NC(GPD9, NONE),
+ /* GPD9: SLP_WLAN_L */
+ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
/* GPD10: SLP_S5# ==> SLP_S5_L */
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* GPD11: LANPHYC ==> NC */
- PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+ PAD_NC(GPD11, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
- /* A7 : MEM_STRAP_0 */
- PAD_CFG_GPI(GPP_A7, NONE, DEEP),
- /* A17 : MEM_CH_SEL */
- PAD_CFG_GPI(GPP_A17, NONE, DEEP),
- /* A19 : MEM_STRAP_2 */
- PAD_CFG_GPI(GPP_A19, NONE, DEEP),
- /* A20 : MEM_STRAP_1 */
- PAD_CFG_GPI(GPP_A20, NONE, DEEP),
- /* D15 : MEM_STRAP_3 */
- PAD_CFG_GPI(GPP_D15, NONE, DEEP),
-
- /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ /* A7 : MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+ /* A12 : M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A17 : MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* A19 : MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+ /* A20 : MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_A20, NONE, DEEP),
- /* B11 : PMCALERT# ==> PCH_WP_OD */
+ /* B11 : PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
- /* E10 : PCH_GSPI0_H1_TPM_CS_L */
- PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
- /* E11 : PCH_GSPI0_H1_TPM_CLK */
- PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
- /* E12 : PCH_GSPIO_H1_TPM_MISO */
- PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
- /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
- PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
- /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
-
+ /* C0 : EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C3 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
- /* D10 : EN_PP3300_WWAN */
- PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ /* D10 : EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ /* D12 : PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_D12, 0, DEEP),
+ /* D15 : MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+ /* D16 : EN_PP3300_SD */
+ PAD_NC(GPP_D16, UP_20K),
+
+ /* E10 : PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
+ /* E11 : PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
+ /* E12 : PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
+ /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
+
+ /* F14 : WLAN_PERST_L */
+ PAD_CFG_GPO(GPP_F14, 1, DEEP),
+ /* F20 : WWAN_RST_ODL
+ To meet timing constrains - drive reset low.
+ Deasserted in ramstage. */
+ PAD_CFG_GPO(GPP_F20, 0, DEEP),
};
const struct pad_config *__weak variant_base_gpio_table(size_t *num)
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