Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu.

Shuo Liu uploaded patch set #4 to this change.

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The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)

soc/intel/xeon_sp: Add soc_add_dram_resources

SoC specific DRAM resource, e.g. 4GB above DRAM memory map, CXL,
et al, are different across SoC generations. This patch separates
the codes so that different SoC generations could have different
implementations.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 69 insertions(+), 44 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/4

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