Patch set 4:Code-Review +2
5 comments:
File src/soc/intel/braswell/Makefile.inc:
Patch Set #3, Line 42: ramstage-y += smbus.c
Since I will use it for SPD retrieval only, I may remove it from ramstage
Ack
File src/soc/intel/braswell/include/soc/smbus.h:
nit: single empty line, please
Done
Patch Set #3, Line 24: #define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC))
I don't think we actually need this. You don't seem to be using the […]
Done
File src/soc/intel/braswell/smbus.c:
Patch Set #3, Line 18: #include <device/pci_def.h>
Yes, for the PCI_BASE_ADDRESS_4, PCI_COMMAND and PCI_COMMAND_IO values
Oh, I'm stupid :-/
/* Disable interrupts */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
/* Clear errors */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
Yes, it clears the errors and interrupts on command setup. I will test without these.
Ack
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