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Patch Set #2, Line 10:
This device gets hidden from PCI bus
in FSP-S
No, in SPT PCH, PWRMBASE and ABASE are at offset 0x44 and 0x48 hence PCI enumeration don't change th […]
"its been recommended" -- by whom?
From coreboot perspective it would have been much cleaner to flag those BARs with ASSIGNED | FIXED in the respective .read_resources. That would have kept them in their pre-programmed values. But.. sounds like the blob takes this "offensive" option.
Is this hiding of PMC forced by FSP (and can you affect future builds to no do that!) ?
PCH_PWRM_BASE_ADDRESS 0xfe000000
I believe that thi is´ below IOAPICs. There is nothing preventing resource allocator from assigning other resources over this, is there?
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