Michał Żygowski has uploaded this change for review.
mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
---
M src/mainboard/amd/db-ft3b-lc/romstage.c
M src/mainboard/amd/inagua/BiosCallOuts.c
M src/mainboard/amd/lamar/romstage.c
M src/mainboard/amd/olivehill/mptable.c
M src/mainboard/amd/olivehill/romstage.c
M src/mainboard/amd/olivehillplus/romstage.c
M src/mainboard/amd/persimmon/BiosCallOuts.c
M src/mainboard/amd/south_station/BiosCallOuts.c
M src/mainboard/amd/thatcher/romstage.c
M src/mainboard/amd/union_station/BiosCallOuts.c
M src/mainboard/asrock/e350m1/BiosCallOuts.c
M src/mainboard/asrock/imb-a180/mptable.c
M src/mainboard/asrock/imb-a180/romstage.c
M src/mainboard/asus/am1i-a/romstage.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/bap/ode_e20XX/romstage.c
M src/mainboard/bap/ode_e21XX/romstage.c
M src/mainboard/biostar/a68n_5200/mptable.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/romstage.c
M src/mainboard/elmex/pcm205400/BiosCallOuts.c
M src/mainboard/gizmosphere/gizmo2/romstage.c
M src/mainboard/hp/abm/mptable.c
M src/mainboard/hp/abm/romstage.c
M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
27 files changed, 102 insertions(+), 332 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37401/1
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 475431e..afc0b73 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -34,8 +35,7 @@
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
hudson_lpc_port80();
@@ -69,6 +69,5 @@
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
}
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index b6267a6..eb9019b 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -54,11 +55,9 @@
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
@@ -135,12 +134,11 @@
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16 |= Data8;
+ /* Get SB MMIO Base (AcpiMmioAddr) */
+ Data8 = pm_io_read8(0x27);
+ Data16 = Data8 << 8;
+ Data8 = pm_io_read8(0x26);
+ Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 4dde4e2..ae0234e 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -38,15 +39,13 @@
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
hudson_lpc_decode();
- outb(0x24, 0xCD6);
- outb(0x01, 0xCD7);
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
+ pm_io_write8(0x24, 1);
+ misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */
+ misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */
hudson_lpc_port80();
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 75d026e..3054eff 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -99,45 +99,7 @@
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
-#if 0
- outb(0x0B, 0xCD6);
- outb(0x02, 0xCD7);
- outb(0x50, 0xCD6);
- outb(0x1F, 0xCD7);
-
- outb(0x48, 0xCD6);
- outb(0xF2, 0xCD7);
-
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
- outb(0xED, 0xCD6);
- outb(0x17, 0xCD7);
-
- *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
- *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
- *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
- *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
- *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
-
- *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
-#endif
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 9a28f98..3eb1f4f 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -30,12 +31,10 @@
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index bb80687..1becf13 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -34,8 +35,7 @@
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
hudson_lpc_port80();
@@ -81,6 +81,5 @@
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
}
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 60ce3ee..23a0e9f 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <stdlib.h>
@@ -60,11 +61,9 @@
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
index ecb7e1c..475ce8b 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.c
+++ b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -54,10 +55,9 @@
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
+ Data8 = pm_io_read8(0x27);
+ Data16 = Data8 << 8;
+ Data8 = pm_io_read8(0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
@@ -135,11 +135,9 @@
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 1d89e4d..ab77cd8 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <console/console.h>
@@ -47,9 +48,7 @@
post_code(0x31);
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
+ pm_io_write8(0xea, 1);
*(u8 *)0xfed80101 = 0x98;
}
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
index ecb7e1c..dc2218a 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.c
+++ b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <southbridge/amd/cimx/sb800/gpio_oem.h>
@@ -54,11 +55,10 @@
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
@@ -135,11 +135,9 @@
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
+ Data16 = Data8 << 8;
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 491027a..cf13382 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <stdlib.h>
@@ -52,11 +53,9 @@
Status = AGESA_SUCCESS;
/* Get SB800 MMIO Base (AcpiMmioAddr) */
- WriteIo8 (0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8 (0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index a3c8e51..fd4dff7 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -100,45 +100,7 @@
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
-#if 0
- outb(0x0B, 0xCD6);
- outb(0x02, 0xCD7);
- outb(0x50, 0xCD6);
- outb(0x1F, 0xCD7);
-
- outb(0x48, 0xCD6);
- outb(0xF2, 0xCD7);
-
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
- outb(0xED, 0xCD6);
- outb(0x17, 0xCD7);
-
- *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
- *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
- *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
- *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
- *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
-
- *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
-#endif
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index ce5e064..139f63d 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -28,9 +29,6 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
- volatile u32 *addr32;
- u32 t32;
-
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
@@ -38,24 +36,16 @@
hudson_lpc_port80();
/* Enable the AcpiMmio space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
- addr32 = (u32 *)0xfed80e28;
- t32 = *addr32;
- t32 &= 0xfff8ffff;
- *addr32 = t32;
+ misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- addr32 = (u32 *)0xfed80e40;
- t32 = *addr32;
- t32 &= 0xffffbffb;
- *addr32 = t32;
+ misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c
index 5e1218a..88b3121 100644
--- a/src/mainboard/asus/am1i-a/romstage.c
+++ b/src/mainboard/asus/am1i-a/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -133,12 +134,10 @@
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xEA, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
/* Set LPC decode enables. */
pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
@@ -147,16 +146,13 @@
hudson_lpc_port80();
/* Enable the AcpiMmio space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
/* Configure ClkDrvStr1 settings */
- addr32 = (u32 *)0xfed80e24;
- *addr32 = 0x030800aa;
+ misc_write32(0x24, 0x030800aa);
/* Configure MiscClkCntl1 settings */
- addr32 = (u32 *)0xfed80e40;
- *addr32 = 0x000c4050;
+ misc_write32(0x40, 0x000c4050);
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index d5acdb5..962d9db 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
#include <console/console.h>
#include <device/pnp_type.h>
#include <device/pci_ops.h>
@@ -30,20 +31,19 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
u32 reg32;
- reg32 = SB_MMIO_MISC32(0x28);
+ reg32 = misc_read32(0x28);
reg32 &= 0xffc7ffff;
reg32 |= 0x00100000;
- SB_MMIO_MISC32(0x28) = reg32;
+ misc_write32(0x28, reg32);
- reg32 = SB_MMIO_MISC32(0x40);
+ reg32 = misc_read32(0x40);
reg32 &= ~0x80u;
- SB_MMIO_MISC32(0x40) = reg32;
+ misc_write32(0x40, reg32);
}
static void superio_init_m(void)
@@ -87,8 +87,7 @@
post_code(0x30);
/* enable SB MMIO space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
/* enable SIO clock */
sbxxx_enable_48mhzout();
@@ -99,10 +98,7 @@
superio_init_m();
/* turn on secondary smbus at b20 */
- outb(0x28, 0xcd6);
- byte = inb(0xcd7);
- byte |= 1;
- outb(byte, 0xcd7);
+ pm_io_write8(0x28, pm_io_read8(0x28) | 1);
/* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index ef7a7fb..e3e0e4d 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_ops.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
@@ -29,8 +30,7 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write(0xea, 1);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index e58f875..a9702de 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <arch/cpu.h>
@@ -38,8 +39,7 @@
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
hudson_lpc_port80();
@@ -74,6 +74,5 @@
post_code(0x41);
AGESAWRAPPER(amdinitenv);
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
}
diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c
index 75d026e..3054eff 100644
--- a/src/mainboard/biostar/a68n_5200/mptable.c
+++ b/src/mainboard/biostar/a68n_5200/mptable.c
@@ -99,45 +99,7 @@
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
-#if 0
- outb(0x0B, 0xCD6);
- outb(0x02, 0xCD7);
- outb(0x50, 0xCD6);
- outb(0x1F, 0xCD7);
-
- outb(0x48, 0xCD6);
- outb(0xF2, 0xCD7);
-
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
- outb(0xED, 0xCD6);
- outb(0x17, 0xCD7);
-
- *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
- *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
- *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
- *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
- *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
-
- *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
-#endif
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
index ddcf4d0..e21c996 100644
--- a/src/mainboard/biostar/a68n_5200/romstage.c
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -16,6 +16,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -24,9 +25,6 @@
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
-#define SB_MMIO 0xFED80000
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
-
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)
@@ -34,16 +32,14 @@
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
- /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
u32 reg32;
- reg32 = SB_MMIO_MISC32(0x28);
+ reg32 = misc_read32(0x28);
reg32 &= 0xfff8ffff;
- SB_MMIO_MISC32(0x28) = reg32;
+ misc_write32(0x28, reg32);
- /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- reg32 = SB_MMIO_MISC32(0x40);
+ reg32 = misc_read32(0x40);
reg32 &= 0xffffbffb;
- SB_MMIO_MISC32(0x40) = reg32;
+ misc_write32(0x40, reg32);
}
void board_BeforeAgesa(struct sysinfo *cb)
@@ -51,8 +47,7 @@
u8 byte;
/* Enable the AcpiMmio space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
/* Set LPC decode enables. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index c83a865..6ea2f28 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <amdblocks/acpimmio.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <console/console.h>
@@ -30,7 +31,6 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void ite_evc_conf(pnp_devfn_t dev)
{
@@ -82,8 +82,7 @@
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
/* Set LPC decode enables. */
pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3);
@@ -92,20 +91,13 @@
hudson_lpc_port80();
/* Enable the AcpiMmio space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24 ,1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
- addr32 = (u32 *)0xfed80e28;
- t32 = *addr32;
- t32 &= 0xfff8ffff;
- *addr32 = t32;
+ misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- addr32 = (u32 *)0xfed80e40;
- t32 = *addr32;
- t32 &= 0xffffbffb;
- *addr32 = t32;
+ misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
@@ -134,8 +126,7 @@
for (i = 0; i < 200000; i++)
val = inb(0xcd6);
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
post_code(0x50);
}
diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
index 6e2eaed..01f06bd 100644
--- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c
+++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c
@@ -15,6 +15,7 @@
#include <AGESA.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <SB800.h>
#include <stdlib.h>
@@ -60,11 +61,9 @@
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16=Data8<<8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16|=Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index c656347..846b57a 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/acpimmio.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -31,21 +32,5 @@
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
}
-
-#if 0
- /* LPC clock? Should happen before enable_serial. */
-
- /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
- int i;
- for(i = 0; i < 200000; i++)
- val = inb(0xcd6);
-#endif
-
-#if 0
- /* Was before copy_and_run. */
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
-#endif
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index 75d026e..3054eff 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -99,45 +99,7 @@
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
-#if 0
- outb(0x0B, 0xCD6);
- outb(0x02, 0xCD7);
- outb(0x50, 0xCD6);
- outb(0x1F, 0xCD7);
-
- outb(0x48, 0xCD6);
- outb(0xF2, 0xCD7);
-
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
- outb(0xED, 0xCD6);
- outb(0x17, 0xCD7);
-
- *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
- *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
- *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
- *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
-
- *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
- *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
- *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
-
- *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
- *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
-
- *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
-#endif
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 2cc8d1b..52bbfbc 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/acpimmio.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
@@ -25,7 +26,6 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
- u32 *addr32;
u32 t32;
/* For serial port option, plug-in card on LPC. */
@@ -39,34 +39,21 @@
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
+ pm_io_write8(0xd2, 0);
/* Enable the AcpiMmio space */
- outb(0x24, 0xcd6);
- outb(0x01, 0xcd7);
+ pm_io_write8(0x24, 1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */
/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
- addr32 = (u32 *)0xfed80e28;
- t32 = *addr32;
+ t32 = misc_read32(0x28);
t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
t32 |= 0x00010000; // Set bit 16 for 25MHz
- *addr32 = t32;
+ misc_write(0x28, t32);
/* Enable Auxiliary OSCOUT1/OSCOUT2 */
- addr32 = (u32 *)0xfed80e40;
- t32 = *addr32;
- t32 &= 0xffffff7b; // clear 2, 7
- *addr32 = t32;
+ t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b);
nct5104d_enable_uartd(SERIAL_DEV);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
-
-#if 0
- /* Was before copy_and_run. */
- outb(0xEA, 0xCD6);
- outb(0x1, 0xcd7);
-#endif
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 86999fb..c2227ae 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -17,6 +17,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <amdlib.h>
+#include <amdblocks/acpimmio.h>
#include <vendorcode/amd/cimx/sb800/SB800.h>
#include <stdint.h>
#include <stdlib.h>
@@ -63,11 +64,9 @@
FcnData = Data;
ResetInfo = ConfigPtr;
/* Get SB800 MMIO Base (AcpiMmioAddr) */
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x27);
Data16 = Data8 << 8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
+ Data8 = pm_io_read8(0x26);
Data16 |= Data8;
AcpiMmioAddr = (uint32_t)Data16 << 16;
Status = AGESA_UNSUPPORTED;
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 0266eff..22da041 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <amdblocks/acpimmio.h>
#include <arch/io.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
@@ -31,7 +32,6 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SUPERIO_ADDRESS 0x4e
@@ -101,14 +101,14 @@
{
/* most likely programming to 48MHz out signal */
u32 reg32;
- reg32 = SB_MMIO_MISC32(0x28);
+ reg32 = misc_read32(0x28);
reg32 &= 0xffc7ffff;
reg32 |= 0x00100000;
- SB_MMIO_MISC32(0x28) = reg32;
+ misc_write32(0x28, reg32);
- reg32 = SB_MMIO_MISC32(0x40);
+ reg32 = misc_read32(0x40);
reg32 &= ~0x80u;
- SB_MMIO_MISC32(0x40) = reg32;
+ misc_write32(0x40, reg32);
}
@@ -136,8 +136,7 @@
post_code(0x30);
/* enable SB MMIO space */
- outb(0x24, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0x24, 1);
/* enable SIO clock */
sbxxx_enable_48mhzout();
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 6c97c57..791afa8 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <amdblocks/acpimmio.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -49,8 +50,7 @@
* the SoC BKDGs. Without this setting, there is no serial
* output.
*/
- outb(0xd2, 0xcd6);
- outb(0x00, 0xcd7);
+ pm_io_write8(0xd2, 0);
hudson_lpc_port80();
@@ -81,8 +81,7 @@
}
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
- outb(0xea, 0xcd6);
- outb(0x1, 0xcd7);
+ pm_io_write8(0xea, 1);
}
static void early_lpc_init(void)
To view, visit change 37401. To unsubscribe, or for help writing mail filters, visit settings.