10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.


soc/intel/meteorlake: Add timestamp for cse_fw_sync

The patch adds timestamp around cse_fw_sync().

BUG=none
TEST=Verified on rex, cbmem -t:

948:starting CSE firmware sync 	1,340,551 (50,657)
949:finished CSE firmware sync 	1,379,348 (38,797)

Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp
for cse_fw_sync")'

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/meteorlake/romstage/romstage.c
1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index bac3caf..ba0079c 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -15,6 +15,7 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
+#include <timestamp.h>
 #include <string.h>
 
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
@@ -130,8 +131,11 @@
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	if (!s3wake) {
-		if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+		if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
+			timestamp_add_now(TS_CSE_FW_SYNC_START);
 			cse_fw_sync();
+			timestamp_add_now(TS_CSE_FW_SYNC_END);
+		}
 	}
 
 	/*

