V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41862 )
Change subject: soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax ......................................................................
soc/intel/jasperlake: Updat scs.asl to ASL2.0 syntax
This change updates scs.asl to use ASL2.0 syntax. This increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/soc/intel/jasperlake/acpi/scs.asl 1 file changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41862/1
diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index bee862d..508fb9b 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -37,22 +37,22 @@ Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us
- Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG
/* Clear register 0x1C20/0x4820 */ SCSC (PID_EMMC)
/* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR }
Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG
/* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR }
Device (CARD) @@ -90,23 +90,23 @@
Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */
/* Clear register 0x1C20/0x4820 */ SCSC (PID_SDX)
/* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR }
Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */
/* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR }
Device (CARD)