[coreboot-gerrit] New patch to review for coreboot: mainboard/intel/kblrvp: Configure usb over current pin & cdclock

[Naresh Solanki]

Naresh Solanki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17251

-gerrit

commit cdde5163b1db6cb0f716acbe6c63a55681cdce39
Author: Naresh G Solanki 
Date:   Sun Nov 6 14:12:55 2016 +0530

mainboard/intel/kblrvp: Configure usb over current pin & cdclock

Configure overcurrent pins for various usb ports.
    Configure CdClock to 3.

Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
    Signed-off-by: Naresh G Solanki 
---
 src/mainboard/intel/kblrvp/ramstage.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index ed37681..6a509b7 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -18,7 +18,19 @@

void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
+	u8 i;
    /* Configure pads prior to SiliconInit() in case there's any
     * dependencies during hardware initialization. */
    gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	params->CdClock = 3;
+
+	/* Set proper OC for various USB ports*/
+	u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8};
+	u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 };
+
+	for (i = 0; i < ARRAY_SIZE(usb2_oc); i++)
+		params->Usb2OverCurrentPin[i] = usb2_oc[i];
+
+	for (i = 0; i < ARRAY_SIZE(usb3_oc); i++)
+		params->Usb3OverCurrentPin[i] = usb3_oc[i];
 }