Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35985 )
Change subject: intel/skylake: Implement PCIe RP devicetree update based on LCAP
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Patch Set 17:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35985/14/src/soc/intel/common/block...
File src/soc/intel/common/block/pcie/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/35985/14/src/soc/intel/common/block...
PS14, Line 28: #define INTEL_RP_CLIST_XCAP 0x40
PS#17 is the alternative
Understood it's vendor code. I was just meaning it the capability offsets could change even with intel's implementations.
https://review.coreboot.org/c/coreboot/+/35985/14/src/soc/intel/common/block...
PS14, Line 47: port_num
Seems correct to me, […]
That's fair. I think I was reading it as a positive as opposed to an error.
https://review.coreboot.org/c/coreboot/+/35985/14/src/soc/intel/common/block...
PS14, Line 97: "Remapping PCIe Root Port #%u from %s to new function number %u.\n",
Why not?
I was meaning should we add it to the message.
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