Patch Set 2:
Patch Set 2:
(3 comments)
Move to cpu/x86? I don't think it is Intel specific.
this is to enable WB capability in caching between romstage end and postcar. you can follow the topic CLs
I understand what these CL are doing and I think it's more generally useable than soc/intel. I have some local patches that lz4 compress postcar which should further speed things up, but for performance reasons decompression needs to happen WB cached.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd
Gerrit-Change-Number: 34992
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
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Gerrit-Comment-Date: Thu, 21 Nov 2019 13:54:24 +0000
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