Patch Set 7:
That AGESA (or any blob) manipulates MTRRs is discouraged and I understand such behaviour was removed for amd/stoneyridge.
Also, src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c shows there is some back-and-forth copying of AGESA heap. The code is form of CAR migration with intermediate buffer kept as uncacheable.
Right. I suppose the commit message is not entirely accurate then. What I meant was that the location where cbmem ends up will be set up as WB by AGESA and that this is recommended if one wants to decompress+clflush postcar (+ other things in cbmem) there.
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