Patch Set 7:

That AGESA (or any blob) manipulates MTRRs is discouraged and I understand such behaviour was removed for amd/stoneyridge.

Also, src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c shows there is some back-and-forth copying of AGESA heap. The code is form of CAR migration with intermediate buffer kept as uncacheable.

Right. I suppose the commit message is not entirely accurate then. What I meant was that the location where cbmem ends up will be set up as WB by AGESA and that this is recommended if one wants to decompress+clflush postcar (+ other things in cbmem) there.

View Change

To view, visit change 37198. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b
Gerrit-Change-Number: 37198
Gerrit-PatchSet: 7
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Marshall Dawson <>
Gerrit-Reviewer: Michał Żygowski <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Krystian Hebel <>
Gerrit-CC: Kyösti Mälkki <>
Gerrit-CC: Mike Banon <>
Gerrit-CC: Paul Menzel <>
Gerrit-Comment-Date: Wed, 27 May 2020 13:27:39 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: No
Gerrit-MessageType: comment