2 comments:
it's actually slower than simply letting FSP (vs coreboot)
read the SPD data via smbus, so drop it.
SPD cache is used not just to speed up boot, but also to decide when memory should be retrained if a DIMM is added/removed. Dropping this support will break that functionality.
Test: build/boot WYVERN variant, check boot times via cbmem:
w/SPD caching: ~722 ms
w/FSP reading: ~627 ms
Adding Jamie Chen who had observed that the SPD cache brought boot time improvements as mentioned in the commit message:
"TEST=Build puff successfully and verified below two items.
1. To change memory DIMM can trigger retraining.
2. one DIMM save the boot time : 158ms
two DIMM save the boot time : 265ms"
I don't understand why there is a difference from original implementation.
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