50 comments:
File src/mainboard/google/volteer/variants/delbin/gpio.c:
/* A9 : I2S2_TXD ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_A9, NONE, DEEP),
Remove this because this is same as baseboard/gpio. […]
Done
/* A11 : PMC_I2C_SDA ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
Remove this
Done
/* A14 : USB_OC1# ==> USB_A0_OC_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# ==> USB_A1_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
Remove this
Done
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
Remove this
Done
/* A21 : DDPC_CTRCLK ==> NC */
PAD_NC(GPP_A21, NONE),
Remove this
Done
/* B0 : CORE_VID0 */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
/* B1 : CORE_VID1 */
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
Remove this
Done
/* B3 : CPU_GP2 ==> NC */
PAD_NC(GPP_B3, NONE),
/* B4 : CPU_GP3 ==> NC */
PAD_NC(GPP_B4, NONE),
/* B5 : ISH_I2C0_CVF_SDA == NC */
PAD_NC(GPP_B5, NONE),
/* B6 : ISH_I2C0_CVF_SCL == NC */
PAD_NC(GPP_B6, NONE),
/* B7 : ISH_12C1_SDA ==> NC */
PAD_NC(GPP_B7, NONE),
/* B8 : ISH_I2C1_SCL ==> NC */
PAD_NC(GPP_B8, NONE),
Remove this
Done
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B12 : SLP_S0# ==> SLP_S0_L */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* B13 : PLTRST# ==> PLT_RST_L */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* B19 : GSPI1_CS0# ==> NC */
PAD_NC(GPP_B19, NONE),
/* B20 : GSPI1_CLK ==> NC */
PAD_NC(GPP_B20, NONE),
/* B21 : GSPI1_MISO ==> NC */
PAD_NC(GPP_B21, NONE),
Remove this
Done
/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
PAD_NC(GPP_B23, NONE),
Remove this
Done
/* C1 : SMBDATA ==> NOT USED */
PAD_NC(GPP_C1, NONE),
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
PAD_NC(GPP_C2, NONE),
/* C3 : SML0CLK ==> NC */
PAD_NC(GPP_C3, NONE),
/* C4 : SML0DATA ==> NC */
PAD_NC(GPP_C4, NONE),
/* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
PAD_NC(GPP_C5, NONE),
/* C6 : SML1CLK ==> EC_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT),
/* C7 : SML1DATA ==> NC */
PAD_NC(GPP_C7, NONE),
/* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
Remove this
Done
/* C11 : UART0_CTS# ==> NC */
PAD_NC(GPP_C11, NONE),
/* C12 : UART1_RXD ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
/* C13 : UART1_TXD ==> NC */
PAD_NC(GPP_C13, NONE),
/* C14 : UART1_RTS# ==> MEM_STRAP_2 */
PAD_CFG_GPI(GPP_C14, NONE, DEEP),
/* C15 : UART1_CTS# ==> MEM_STRAP_1 */
PAD_CFG_GPI(GPP_C15, NONE, DEEP),
Remove this
Done
/* C20 : UART2_RXD ==> NC */
PAD_NC(GPP_C20, NONE),
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : UART2_RTS# ==> NC */
PAD_NC(GPP_C22, NONE),
/* C23 : UART2_CTS# ==> NC */
PAD_NC(GPP_C23, NONE),
Remove this
Done
/* D0 : ISH_GP0 ==> NC */
PAD_NC(GPP_D0, NONE),
/* D1 : ISH_GP1 ==> NC */
PAD_NC(GPP_D1, NONE),
/* D2 : ISH_GP2 ==> NC */
PAD_NC(GPP_D2, NONE),
/* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE),
/* D4 : IMGCLKOUT0 ==> NC */
PAD_NC(GPP_D4, NONE),
/* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */
PAD_NC(GPP_D6, NONE),
/* D7 : SRCCLKREQ2# ==> NC */
PAD_NC(GPP_D7, NONE),
Remove this
Done
/* D9 : ISH_SPI_CS# ==> NC */
PAD_NC(GPP_D9, NONE),
Remove this
Done
/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7),
Remove this. […]
Done
/* D11 : ISH_SPI_MISO ==> NC */
PAD_NC(GPP_D11, NONE),
Remove this
Done
/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
Remove this. […]
Done
/* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */
PAD_CFG_GPI(GPP_D15, NONE, DEEP),
Remove this
Done
/* D18 : ISH_GP5 ==> NC */
PAD_NC(GPP_D18, NONE),
/* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
Remove this
Done
/* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
PAD_CFG_GPO(GPP_E0, 1, DEEP),
/* E1 : SPI1_IO2 ==> NC */
PAD_NC(GPP_E1, NONE),
/* E2 : SPI1_IO3 ==> NC */
PAD_NC(GPP_E2, NONE),
Remove this
Done
/* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
PAD_NC(GPP_E6, NONE),
Remove this
Done
/* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF6),
Remove this
Done
/* E12 : SPI1_MISO_IO1 ==> NC */
PAD_NC(GPP_E12, NONE),
/* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF6),
/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
Remove this
Done
/* E16 : ISH_GP7 ==> NC */
PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE),
Remove this
Done
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
Remove this
Done
/* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
/* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
PAD_NC(GPP_E22, NONE),
/* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
PAD_NC(GPP_E23, NONE),
Remove this
Done
/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
/* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
/* F3 : I2S2_RXD ==> CNV_RGI_RSP */
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
/* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
/* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE),
/* F7 : GPPF7_STRAP */
PAD_NC(GPP_F7, NONE),
Remove this
Done
/* F9 : Reserved ==> NC */
PAD_NC(GPP_F9, NONE),
/* F10 : GPPF10_STRAP */
PAD_NC(GPP_F10, DN_20K),
Remove this
Done
/* F12 : GSXDOUT ==> NC */
PAD_NC(GPP_F12, NONE),
Remove this
Done
/* F14 : GSXDIN ==> NC */
PAD_NC(GPP_F14, NONE),
/* F15 : GSXSRESET# ==> NC */
PAD_NC(GPP_F15, NONE),
/* F16 : GSXCLK ==> NC */
PAD_NC(GPP_F16, NONE),
/* F17 : WWAN_RF_DISABLE_ODL == NC */
PAD_NC(GPP_F17, NONE),
/* F18 : THC1_SPI2_INT# ==> NC */
PAD_NC(GPP_F18, NONE),
/* F19 : SRCCLKREQ6# ==> NC */
PAD_NC(GPP_F19, NONE),
/* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : VNN_CTRL */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* F23 : V1P05_CTRL */
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
Remove this
Done
/* H0 : GPPH0_BOOT_STRAP1 */
PAD_NC(GPP_H0, NONE),
/* H1 : GPPH1_BOOT_STRAP2 */
PAD_NC(GPP_H1, NONE),
/* H2 : GPPH2_BOOT_STRAP3 */
PAD_NC(GPP_H2, NONE),
Remove this
Done
/* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H6 : I2C3_SDA ==> NC */
PAD_NC(GPP_H6, NONE),
/* H7 : I2C3_SCL ==> NC */
PAD_NC(GPP_H7, NONE),
Remove this
Done
/* H11 : SRCCLKREQ5# ==> NC */
PAD_NC(GPP_H11, NONE),
/* H12 : M2_SKT2_CFG0 ==> NC */
PAD_NC(GPP_H12, NONE),
Remove this
Done
/* H14 : M2_SKT2_CFG2 # ==> NC */
PAD_NC(GPP_H14, NONE),
/* H15 : M2_SKT2_CFG3 # ==> NC */
PAD_NC(GPP_H15, NONE),
Remove this
Done
/* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19 : TIME_SYNC0 ==> NC */
PAD_NC(GPP_H19, NONE),
/* H20 : IMGCLKOUT1 ==> NC */
PAD_NC(GPP_H20, NONE),
/* H21 : IMGCLKOUT2 ==> NC */
PAD_NC(GPP_H21, NONE),
/* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE),
/* H23 : IMGCLKOUT4 ==> NC */
PAD_NC(GPP_H23, NONE),
Remove this
Done
/* R4 : HDA_RST# ==> NC */
PAD_NC(GPP_R4, NONE),
Remove this
Done
/* S4 : SNDW2_CLK ==> NC */
PAD_NC(GPP_S4, NONE),
/* S5 : SNDW2_DATA ==> NC */
PAD_NC(GPP_S5, NONE),
Remove this
Done
/* GPD0: BATLOW# ==> BATLOW_L */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* GPD1: ACPRESENT ==> PCH_ACPRESENT */
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
/* GPD4: SLP_S3# ==> SLP_S3_L */
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* GPD5: SLP_S4# ==> SLP_S4_L */
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* GPD6: SLP_A# ==> SLP_A_L */
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
/* GPD7: GPD7_STRAP */
PAD_CFG_GPI(GPD7, DN_20K, DEEP),
/* GPD8: SUSCLK ==> PCH_SUSCLK */
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
Remove this
Done
/* GPD10: SLP_S5# ==> SLP_S5_L */
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* GPD11: LANPHYC ==> NC */
Remove this
Done
Remove this line
Done
Remove this line
Done
Remove this line
Done
Remove this line
Done
Remove this line
Done
Remove this line
Done
Patch Set #7, Line 430: gpio_table
rename to override_gpio_table to align with the other project like variant/volteer/gpio. […]
Done
File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Headset Codec""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on
probe AUDIO MAX98357_ALC5682I_I2S
probe AUDIO MAX98373_ALC5682I_I2S
end
end
remove this. You're using max98373 according to the schematic.
Done
chip drivers/i2c/sx9310
register "desc" = ""SAR0 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "0"
register "reg_prox_ctrl0" = "0x10"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
register "reg_prox_ctrl7" = "0x0d"
register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x1f"
register "reg_prox_ctrl11" = "0x00"
register "reg_prox_ctrl12" = "0x00"
register "reg_prox_ctrl13" = "0x00"
register "reg_prox_ctrl14" = "0x00"
register "reg_prox_ctrl15" = "0x00"
register "reg_prox_ctrl16" = "0x00"
register "reg_prox_ctrl17" = "0x00"
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
register "reg_sar_ctrl1" = "0x8a"
register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
remove this. I don't see the proximity sensor in the schematic.
Done
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "sdmode_delay" = "5"
device generic 0 on
probe AUDIO MAX98357_ALC5682I_I2S
end
end
chip drivers/intel/soundwire
device generic 0 on
probe AUDIO MAX98373_ALC5682_SNDW
chip drivers/soundwire/alc5682
# SoundWire Link 0 ID 1
register "desc" = ""Headset Codec""
device generic 0.1 on end
end
chip drivers/soundwire/max98373
# SoundWire Link 1 ID 3
register "desc" = ""Left Speaker Amp""
device generic 1.3 on end
end
chip drivers/soundwire/max98373
# SoundWire Link 1 ID 7
register "desc" = ""Right Speaker Amp""
device generic 1.7 on end
end
end
end
remove this. I don't see the sound wire in the schematic.
Done
same as above.
Done
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