Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/23487
Change subject: nb/intel/*.h: Remove left-over register definitions ......................................................................
nb/intel/*.h: Remove left-over register definitions
The code has been moved into drivers folder.
Change-Id: I122affffd5108052ed7a95b34d0d66a6d3279d41 Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/northbridge/intel/fsp_sandybridge/northbridge.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h 4 files changed, 0 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/23487/1
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index c0194f2..ddd56e1 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -105,13 +105,6 @@
#define BCTRL1 0x3e /* 16bit */
- -/* Device 0:2.0 PCI configuration space (Graphics Device) */ - -#define MSAC 0x62 /* Multi Size Aperture Control */ -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* * MCHBAR */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 2d03a68..cd6a537 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -92,13 +92,6 @@
#define BCTRL1 0x3e /* 16bit */
- -/* Device 0:2.0 PCI configuration space (Graphics Device) */ - -#define MSAC 0x62 /* Multi Size Aperture Control */ -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* * MCHBAR */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index a693e12..886cd00 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -191,13 +191,6 @@
#define BCTRL1 0x3e /* 16bit */
- -/* Device 0:2.0 PCI configuration space (Graphics Device) */ - -#define MSAC 0x62 /* Multi Size Aperture Control */ -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* * MCHBAR */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1f56585..591cc3f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -110,13 +110,6 @@
#define BCTRL1 0x3e /* 16bit */
- -/* Device 0:2.0 PCI configuration space (Graphics Device) */ - -#define MSAC 0x62 /* Multi Size Aperture Control */ -#define SWSCI 0xe8 /* SWSCI enable */ -#define ASLS 0xfc /* OpRegion Base */ - /* * MCHBAR */