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3 comments:

• File src/soc/intel/xeon_sp/gnr/chipset.cb:

  • Patch Set #53, Line 10: .chipset_lockdown = CHIPSET_LOCKDOWN_FSP,

    In a server platform many silicon specific register lock ops are by default in FSP space, hence we s […]

    I'm OK with temporarily using FSP lockdown, as it simplifies initial bring-up. But I believe it's best to switch to coreboot lockdown in the long run.

  • Patch Set #53, Line 18: ibl

    Out of curiosity, what does "ibl" mean?

  • Patch Set #53, Line 19: HEPT

    typo: HPET

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