V Sowmya has uploaded this change for review.

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mb/google/hatch: Add the USB port configuration

This patch adds the configurations for,
* USB 2.0 ports
* USB 3.0 ports
* Enables USB xHCI controller
* GPIO config for USB2_OC2 and USB2_OC3

Change-Id: Ia7b25c25b8208c678aeae3a32033611b69b54062
Signed-off-by: V Sowmya <v.sowmya@intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 22 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30457/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 1600be9..352f8ea 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -49,6 +49,23 @@
         register "SataPortsDevSlp[1]" = "1"
         register "satapwroptimize" = "1"
 
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
+	register "usb2_ports[2]" = "USB2_PORT_LONG(OC3)"        # Type-A Port 0
+	register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)"        # Type-A Port 1
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# WLAN and BT
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
+	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C Port 1
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"     # Type-A Port 0
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"     # Type-A Port 1
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Enable Root port 9(x4) for NVMe.
 	# Enable CLKREQ#
@@ -58,9 +75,6 @@
 	# ClkReq-to-ClkSrc mapping for CLK SRC 1
 	register "PcieClkSrcClkReq[1]" = "1"
 
-	# USB PORT 5 for BT and WLAN
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
-
 	# PCIe port 13 for M.2 E-key WLAN
 	register "PcieRpEnable[13]" = "1"
 	register "PcieClkSrcUsage[3]" = "9"
@@ -73,7 +87,7 @@
 		device pci 12.0 off end # Thermal Subsystem
 		device pci 12.5 off end # UFS SCS
 		device pci 12.6 off end # GSPI #2
-		device pci 14.0 off end # USB xHCI
+		device pci 14.0 on  end # USB xHCI TODO: Configure ACPI entries
 		device pci 14.1 off end # USB xDCI (OTG)
 		chip drivers/intel/wifi
                         register "wake" = "GPE0_PME_B0"
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 728fe11..5daaad4 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -68,6 +68,10 @@
 	PAD_CFG_GPO(GPP_E4, 1, DEEP),
 	/* SATA_DEVSLP1 */
 	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+	/* USB_C_OC_OD USB_OC2*/
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* USB_A_OC_OD USB_OC3*/
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 	/* USB_C0_DP_HPD */
 	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 	/* DDI2_HPD_ODL */

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