Patrick Rudolph has uploaded this change for review.

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cpu/x86/sipi_vector: Use spinlock

Change-Id: I3ea5ea370dc75af3544ec903bd9b18399113dec1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/cpu/x86/sipi_vector_c_handler.c
1 file changed, 6 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47710/1

diff --git a/src/cpu/x86/sipi_vector_c_handler.c b/src/cpu/x86/sipi_vector_c_handler.c
index fa11748..47cd11a 100644
--- a/src/cpu/x86/sipi_vector_c_handler.c
+++ b/src/cpu/x86/sipi_vector_c_handler.c
@@ -6,11 +6,14 @@
 #include <arch/cpu.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/amd/mtrr.h>
+#include <smp/spinlock.h>
 
 asmlinkage void sipi_secondary_early_entry(struct sipi_params *const params, int cpu_num);
 
 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW)
 
+DECLARE_SPIN_LOCK(microcode_lock)
+
 static void sipi_update_microcode(struct sipi_params *params)
 {
 	/* Determine if one should check microcode versions. */
@@ -25,23 +28,15 @@
 		return;
 
 	/* Determine if parallel microcode loading is allowed. */
-	if (params->microcode_lock != 0xffffffff) {
-
-		/* Protect microcode loading. */
-		asm volatile(
-		    "\tlock_microcode:\n"
-		    "\tlock bts $0, %0\n"
-		    "\tjc	lock_microcode\n"
-		: "=m"(params->microcode_lock)
-		: "m"(params->microcode_lock));
-	}
+	if (params->microcode_lock != 0xffffffff)
+		spin_lock(&microcode_lock);
 
 	/* Load new microcode. */
 	intel_microcode_load_unlocked((void *)((uintptr_t)params->microcode_ptr));
 
 	/* Unconditionally unlock microcode loading. */
 	if (params->microcode_lock != 0xffffffff)
-		params->microcode_lock = 0;
+		spin_unlock(&microcode_lock);
 }
 
 static void sipi_set_mtrrs(const struct sipi_params *const params)

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