Sathyanarayana Nujella would like HARSHAPRIYA N to review this change.
mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0.
So, enable the pins accordingly.
BUG=b:113744731
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image
Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/gpio.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28433/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 782ce00..08bb801 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -199,10 +199,10 @@
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : DMIC_DATA1 ==> PCH_DMIC_DATA */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
- /* D19 : DMIC_CLK0 ==> NC */
- PAD_CFG_NC(GPP_D19),
- /* D20 : DMIC_DATA0 ==> NC */
- PAD_CFG_NC(GPP_D20),
+ /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* D21 : SPI1_IO2 ==> NC */
PAD_CFG_NC(GPP_D21),
/* D22 : SPI1_IO3 ==> NC */
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