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Patch set 9:Code-Review -1
3 comments:
File src/mainboard/msi/ms7707/romstage.c:
Patch Set #8, Line 56: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);
only required if HWM is accessed in romstage
Ack
Patch Set #8, Line 88: pnp_write_config(dev, 0x27, 0x10); // PWOK follows Intel sequence
Should be part of devicetree
I've fought a lot with this. It did not work in devicetree at all in the beginning. Now it mysteriously does and i can just guess it was the initial 'LPC IF Enables Register' that had both CNF2_LPC_EN (4E/4F) and CNF1_LPC_EN (2E/2F) enabled at the same time and coreboot enabled the wrong confmode.
Patch Set #8, Line 99: pnp_write_config(dev, 0xd0, 0x20); // GPIO2 Output Enable
do you need superio GPIOs for raminit? […]
Ack
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