V Sowmya uploaded patch set #3 to this change.

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mb/intel/jslrvp: Modify the flash layout for fsp debug build

Current flash layout doesn't support the fsp debug builds since
the FW_MAIN_A/B doesn't have enough space to hold the fsp debug
binaries along with ME RW binaries.
This patch reduces the SI_ALL size to 3.5MiB and increase the
SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries.

BRANCH=dedede
TEST=Build and Boot jslrvp with fsp debug enabled Coreboot.

Cq-Depend: chrome-internal:3425366
Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
---
M src/mainboard/intel/jasperlake_rvp/chromeos.fmd
1 file changed, 25 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48154/3

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