Angel Pons submitted this change.
nb/intel/x4x: Clean up DMIBAR/EPBAR definitions
Several registers have been copy-pasted from i945 and do not exist on
Eagle Lake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/x4x.h
2 files changed, 92 insertions(+), 44 deletions(-)
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 81752cd..279a38f 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -60,59 +60,59 @@
u32 reg32;
/* VC0: TC0 only */
- EPBAR8(0x14) = 1;
- EPBAR8(0x4) = 1;
+ EPBAR8(EPVC0RCTL) = 1;
+ EPBAR8(EPPVCCAP1) = 1;
switch (MCHBAR32(0xc00) & 0x7) {
case 0x0:
/* FSB 1066 */
- EPBAR32(0x2c) = 0x0001a6db;
+ EPBAR32(EPVC1ITC) = 0x0001a6db;
break;
case 0x2:
/* FSB 800 */
- EPBAR32(0x2c) = 0x00014514;
+ EPBAR32(EPVC1ITC) = 0x00014514;
break;
default:
case 0x4:
/* FSB 1333 */
- EPBAR32(0x2c) = 0x00022861;
+ EPBAR32(EPVC1ITC) = 0x00022861;
break;
}
- EPBAR32(0x28) = 0x0a0a0a0a;
- EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2;
- EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000;
+ EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
+ EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2;
+ EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000;
MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
/* VC1: ID1, TC7 */
- reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
+ reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xfe) | (1 << 7);
- EPBAR32(0x20) = reg32;
+ EPBAR32(EPVC1RCTL) = reg32;
/* Init VC1 port arbitration table */
- EPBAR32(0x100) = 0x001000001;
- EPBAR32(0x104) = 0x000040000;
- EPBAR32(0x108) = 0x000001000;
- EPBAR32(0x10c) = 0x000000040;
- EPBAR32(0x110) = 0x001000001;
- EPBAR32(0x114) = 0x000040000;
- EPBAR32(0x118) = 0x000001000;
- EPBAR32(0x11c) = 0x000000040;
+ EPBAR32(EP_PORTARB(0)) = 0x001000001;
+ EPBAR32(EP_PORTARB(1)) = 0x000040000;
+ EPBAR32(EP_PORTARB(2)) = 0x000001000;
+ EPBAR32(EP_PORTARB(3)) = 0x000000040;
+ EPBAR32(EP_PORTARB(4)) = 0x001000001;
+ EPBAR32(EP_PORTARB(5)) = 0x000040000;
+ EPBAR32(EP_PORTARB(6)) = 0x000001000;
+ EPBAR32(EP_PORTARB(7)) = 0x000000040;
/* Load table */
- reg32 = EPBAR32(0x20) | (1 << 16);
- EPBAR32(0x20) = reg32;
+ reg32 = EPBAR32(EPVC1RCTL) | (1 << 16);
+ EPBAR32(EPVC1RCTL) = reg32;
asm("nop");
- EPBAR32(0x20) = reg32;
+ EPBAR32(EPVC1RCTL) = reg32;
/* Wait for table load */
- while ((EPBAR8(0x26) & (1 << 0)) != 0)
+ while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0)
;
/* VC1: enable */
- EPBAR32(0x20) |= 1 << 31;
+ EPBAR32(EPVC1RCTL) |= 1 << 31;
/* Wait for VC1 */
- while ((EPBAR8(0x26) & (1 << 1)) != 0)
+ while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0)
;
printk(BIOS_DEBUG, "Done Egress Port\n");
@@ -125,12 +125,12 @@
/* Assume IGD present */
/* Clear error status */
- DMIBAR32(0x1c4) = 0xffffffff;
- DMIBAR32(0x1d0) = 0xffffffff;
+ DMIBAR32(DMIUESTS) = 0xffffffff;
+ DMIBAR32(DMICESTS) = 0xffffffff;
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1;
- DMIBAR8(0x4) = 1;
+ DMIBAR8(DMIPVCCAP1) = 1;
/* VC1: ID1, TC7 */
reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
@@ -203,17 +203,17 @@
/* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
- while ((DMIBAR32(0x26) & (1 << 1)) != 0)
+ while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0)
;
printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */
DMIBAR32(0x200) &= ~(0x3 << 26);
DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
- DMIBAR32(0x88) &= ~0x3;
- DMIBAR32(0x88) |= 0x3;
- /* FIXME: Do we need to read RCBA16(0x88)? */
- DMIBAR16(0x88);
+ DMIBAR32(DMILCTL) &= ~0x3;
+ DMIBAR32(DMILCTL) |= 0x3;
+ /* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */
+ DMIBAR16(DMILCTL);
}
static void x4x_prepare_resume(int s3resume)
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index ff157ad..c624287 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -93,14 +93,42 @@
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
-#define DMIVC0RCTL 0x14
-#define DMIVC1RCTL 0x20
-#define DMIVC1RSTS 0x26
-#define DMIESD 0x44
-#define DMILE1D 0x50
-#define DMILE1A 0x58
-#define DMILE2D 0x60
-#define DMILE2A 0x68
+#define DMIVCECH 0x000 /* 32bit */
+#define DMIPVCCAP1 0x004 /* 32bit */
+
+#define DMIVC0RCAP 0x010 /* 32bit */
+#define DMIVC0RCTL 0x014 /* 32bit */
+#define DMIVC0RSTS 0x01a /* 16bit */
+#define VC0NP (1 << 1)
+
+#define DMIVC1RCAP 0x01c /* 32bit */
+#define DMIVC1RCTL 0x020 /* 32bit */
+#define DMIVC1RSTS 0x026 /* 16bit */
+#define VC1NP (1 << 1)
+
+#define DMIVCPRCAP 0x028 /* 32bit */
+#define DMIVCPRCTL 0x02c /* 32bit */
+#define DMIVCPRSTS 0x032 /* 16bit */
+#define VCPNP (1 << 1)
+
+#define DMIVCMRCAP 0x034 /* 32bit */
+#define DMIVCMRCTL 0x038 /* 32bit */
+#define DMIVCMRSTS 0x03e /* 16bit */
+#define VCMNP (1 << 1)
+
+#define DMIESD 0x044 /* 32bit */
+
+#define DMILE1D 0x050 /* 32bit */
+#define DMILE1A 0x058 /* 64bit */
+#define DMILE2D 0x060 /* 32bit */
+#define DMILE2A 0x068 /* 64bit */
+
+#define DMILCAP 0x084 /* 32bit */
+#define DMILCTL 0x088 /* 16bit */
+#define DMILSTS 0x08a /* 16bit */
+
+#define DMIUESTS 0x1c4 /* 32bit */
+#define DMICESTS 0x1d0 /* 32bit */
/*
* EPBAR
@@ -110,10 +138,30 @@
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
-#define EPESD 0x44
-#define EPLE1D 0x50
-#define EPLE1A 0x58
-#define EPLE2D 0x60
+#define EPPVCCAP1 0x004 /* 32bit */
+#define EPPVCCTL 0x00c /* 32bit */
+
+#define EPVC0RCAP 0x010 /* 32bit */
+#define EPVC0RCTL 0x014 /* 32bit */
+#define EPVC0RSTS 0x01a /* 16bit */
+
+#define EPVC1RCAP 0x01c /* 32bit */
+#define EPVC1RCTL 0x020 /* 32bit */
+#define EPVC1RSTS 0x026 /* 16bit */
+
+#define EPVC1MTS 0x028 /* 32bit */
+#define EPVC1ITC 0x02c /* 32bit */
+
+#define EPESD 0x044 /* 32bit */
+
+#define EPLE1D 0x050 /* 32bit */
+#define EPLE1A 0x058 /* 64bit */
+#define EPLE2D 0x060 /* 32bit */
+#define EPLE2A 0x068 /* 64bit */
+
+#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */
+
+
#define NOP_CMD 0x2
#define PRECHARGE_CMD 0x4
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