Martin L Roth has uploaded this change for review.
src: Add and use POST_BOOTBLOCK_C_ENTRY
Add a notification for entering the bootblock C code. This was already
present on one platform, but this patch defines that and uses it in
all of the bootblock_c_entry() functions.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I45a86ece016e098ca42a31207fdedda5c49708d7
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/cpu/intel/car/bootblock.c
M src/cpu/qemu-x86/bootblock.c
M src/drivers/amd/agesa/bootblock.c
M src/soc/amd/common/block/cpu/noncar/bootblock.c
M src/soc/amd/stoneyridge/bootblock.c
M src/soc/intel/alderlake/bootblock/bootblock.c
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/braswell/bootblock/bootblock.c
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/elkhartlake/bootblock/bootblock.c
M src/soc/intel/icelake/bootblock/bootblock.c
M src/soc/intel/jasperlake/bootblock/bootblock.c
M src/soc/intel/meteorlake/bootblock/bootblock.c
M src/soc/intel/quark/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/xeon_sp/bootblock.c
18 files changed, 70 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/71593/1
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h
index d838815..7fbc60a 100644
--- a/src/commonlib/include/commonlib/console/post_codes.h
+++ b/src/commonlib/include/commonlib/console/post_codes.h
@@ -35,6 +35,13 @@
*/
#define POST_RESET_VECTOR_CORRECT 0x01
+
+/**
+ * \brief Entry into bootblock_c_entry_bist or bootblock_c_entry
+ *
+ */
+#define POST_BOOTBLOCK_C_ENTRY 0x05
+
/**
* \brief Entry into protected mode
*
diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c
index c53379b..49fb86d 100644
--- a/src/cpu/intel/car/bootblock.c
+++ b/src/cpu/intel/car/bootblock.c
@@ -2,6 +2,7 @@
#include <arch/bootblock.h>
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <cpu/x86/bist.h>
#include <stdint.h>
@@ -9,6 +10,8 @@
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
saved_bist = bist;
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c
index 1b46403e..514622f 100644
--- a/src/cpu/qemu-x86/bootblock.c
+++ b/src/cpu/qemu-x86/bootblock.c
@@ -1,12 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
- post_code(0x05);
+ post_code(POST_BOOTBLOCK_C_ENTRY);
/* Halt if there was a built in self test failure */
if (bist) {
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c
index df9876a..e287793 100644
--- a/src/drivers/amd/agesa/bootblock.c
+++ b/src/drivers/amd/agesa/bootblock.c
@@ -5,6 +5,7 @@
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/biosram.h>
#include <arch/bootblock.h>
+#include <commonlib/console/post_codes.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic.h>
@@ -25,6 +26,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
enable_pci_mmconf();
set_early_mtrrs();
diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c
index 13bac18..d4a484e 100644
--- a/src/soc/amd/common/block/cpu/noncar/bootblock.c
+++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c
@@ -3,6 +3,7 @@
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/cpu.h>
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/tsc.h>
@@ -12,6 +13,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
early_cache_setup();
write_resume_eip();
enable_pci_mmconf();
diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
index f5451f85..f8a8dc2 100644
--- a/src/soc/amd/stoneyridge/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -14,6 +14,7 @@
#include <amdblocks/biosram.h>
#include <amdblocks/iomap.h>
#include <amdblocks/post_codes.h>
+#include <commonlib/console/post_codes.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
#include <soc/southbridge.h>
@@ -58,6 +59,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
enable_pci_mmconf();
amd_initmmio();
/*
diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c
index b8086a4..44a95d7 100644
--- a/src/soc/intel/alderlake/bootblock/bootblock.c
+++ b/src/soc/intel/alderlake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
@@ -9,6 +10,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index c9b6d93..3630ed8 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <cpu/x86/pae.h>
#include <device/pci.h>
#include <device/pci_ops.h>
@@ -40,6 +41,7 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
pci_devfn_t dev;
+ post_code(POST_BOOTBLOCK_C_ENTRY);
bootblock_systemagent_early_init();
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 545642f..c5ae330 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -3,6 +3,7 @@
#include <arch/io.h>
#include <bootblock_common.h>
#include <build.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <fsp/util.h>
@@ -17,6 +18,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index a138ec4..0e12e91 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
@@ -13,6 +14,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 0846c8e..bdeeac3 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -2,6 +2,7 @@
#include <assert.h>
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <FsptUpd.h>
@@ -48,6 +49,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
};
diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c
index cc0bb8f..5de1c54 100644
--- a/src/soc/intel/elkhartlake/bootblock/bootblock.c
+++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
@@ -11,6 +12,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c
index ef5ada6..160cf64 100644
--- a/src/soc/intel/icelake/bootblock/bootblock.c
+++ b/src/soc/intel/icelake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
@@ -9,6 +10,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c
index b8086a4..44a95d7 100644
--- a/src/soc/intel/jasperlake/bootblock/bootblock.c
+++ b/src/soc/intel/jasperlake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
@@ -9,6 +10,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/meteorlake/bootblock/bootblock.c b/src/soc/intel/meteorlake/bootblock/bootblock.c
index c7e1826..d4dac73 100644
--- a/src/soc/intel/meteorlake/bootblock/bootblock.c
+++ b/src/soc/intel/meteorlake/bootblock/bootblock.c
@@ -1,10 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <soc/bootblock.h>
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c
index 2e1a099..4fd83be 100644
--- a/src/soc/intel/quark/bootblock/bootblock.c
+++ b/src/soc/intel/quark/bootblock/bootblock.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <device/pci_def.h>
@@ -65,6 +66,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
light_sd_led();
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 4b31f77..3dc86a3 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <cpu/cpu.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
@@ -11,6 +12,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/* Call lib/bootblock.c main */
bootblock_main_with_basetime(base_timestamp);
}
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 5ea09ac..e975b18 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
+#include <commonlib/console/post_codes.h>
#include <device/pci.h>
#include <FsptUpd.h>
#include <intelblocks/fast_spi.h>
@@ -39,6 +40,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
+ post_code(POST_BOOTBLOCK_C_ENTRY);
+
/*
* FSP-T does not respect its own API and trashes registers
* coreboot uses to store its initial timestamp.
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