Meera Ravindranath has uploaded this change for review.
mb/google/dedede: Add Jasper Lake memory initialization support
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST= Build dedede, flash and boot to kernel
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Makefile.inc
M src/mainboard/google/dedede/romstage.c
A src/mainboard/google/dedede/spd/Makefile.inc
A src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
A src/mainboard/google/dedede/spd/empty.spd.hex
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
A src/mainboard/google/dedede/variants/waddledoo/memory.c
9 files changed, 230 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/39136/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 3eddabc..43c104b 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -13,6 +13,7 @@
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_JASPERLAKE
+ select GENERIC_SPD_BIN
if BOARD_GOOGLE_BASEBOARD_DEDEDE
@@ -68,4 +69,8 @@
default "dedede" if BOARD_GOOGLE_DEDEDE
default "waddledoo" if BOARD_GOOGLE_WADDLEDOO
+config DIMM_SPD_SIZE
+ int
+ default 512
+
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc
index 2be3feb..9af93dd 100644
--- a/src/mainboard/google/dedede/Makefile.inc
+++ b/src/mainboard/google/dedede/Makefile.inc
@@ -13,6 +13,8 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
subdirs-y += variants/baseboard
+subdirs-y += spd
+
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c
index bba6e1a..ce014bb 100644
--- a/src/mainboard/google/dedede/romstage.c
+++ b/src/mainboard/google/dedede/romstage.c
@@ -1,15 +1,24 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors.
+ * Copyright (C) 2020 Intel Corporation.
*
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+*/
-#include <fsp/api.h>
+#include <baseboard/variants.h>
+#include <soc/jsl_memcfg_init.h>
#include <soc/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
- /* ToDo : Fill FSP-M memory params */
+ jasperlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config());
}
+
diff --git a/src/mainboard/google/dedede/spd/Makefile.inc b/src/mainboard/google/dedede/spd/Makefile.inc
new file mode 100644
index 0000000..97a4dfd
--- /dev/null
+++ b/src/mainboard/google/dedede/spd/Makefile.inc
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ifneq ($(SPD_SOURCES),)
+SPD_BIN = $(obj)/spd.bin
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
+endif
diff --git a/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
new file mode 100644
index 0000000..71e5456
--- /dev/null
+++ b/src/mainboard/google/dedede/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00
+00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dedede/spd/empty.spd.hex b/src/mainboard/google/dedede/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/google/dedede/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
index 32b2c8b..4987bb2 100644
--- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
@@ -27,5 +27,5 @@
* @return 0 on success or negative integer for errors.
*/
int board_info_get_fw_config(uint32_t *fw_config);
-
+const struct jsl_mb_cfg *variant_memcfg_config(void);
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
new file mode 100644
index 0000000..4f3b453
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2020 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = empty # 0b000
+SPD_SOURCES += empty # 1b001
+SPD_SOURCES += Micron_MT53E512M32D2NP_2GB
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory.c b/src/mainboard/google/dedede/variants/waddledoo/memory.c
new file mode 100644
index 0000000..b00ab86
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/waddledoo/memory.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/jsl_memcfg_init.h>
+#include <soc/romstage.h>
+
+static const struct jsl_mb_cfg baseboard_memcfg_cfg = {
+ /* Access memory info through SMBUS. */
+
+ .spd[0] = {
+ .read_type = READ_SPD_CBFS,
+ .spd_spec = {.spd_index = 0x2}
+ },
+ .spd[2] = {
+ .read_type = READ_SPD_CBFS,
+ .spd_spec = {.spd_index = 0x2}
+ },
+
+ .dq_map[DDR_CH0] = {
+ {0xf, 0xf0},
+ {0xf, 0xf0},
+ {0xff, 0x0},
+ {0x0, 0x0},
+ {0x0, 0x0},
+ {0x0, 0x0}
+ },
+ .dq_map[DDR_CH1] = {
+ {0xf, 0xf0},
+ {0xf, 0xf0},
+ {0xff, 0x0},
+ {0x0, 0x0},
+ {0x00, 0x0},
+ {0x00, 0x0}
+ },
+
+ /*
+ * The dqs_map arrays map the ddr4 pins to the SoC pins
+ * for both channels.
+ *
+ * the index = pin number on ddr4 part
+ * the value = pin number on SoC
+ */
+ .dqs_map[DDR_CH0] = {1, 3, 0, 2, 7, 5, 4, 6},
+ .dqs_map[DDR_CH1] = {3, 1, 2, 0, 4, 5, 7, 6},
+
+ /* Baseboard uses 100, 100 and 100 rcomp resistors */
+ .rcomp_resistor = {100, 100, 100},
+
+ /*
+ * Baseboard Rcomp target values.
+ */
+ .rcomp_targets = {80, 40, 40, 40, 30},
+
+ /* Baseboard is an interleaved design */
+ .dq_pins_interleaved = 0,
+
+ /* Baseboard is using config 2 for vref_ca */
+ .vref_ca_config = 2,
+
+ /* Disable Early Command Training */
+ .ect = 1,
+
+ /* User Board Type */
+ .UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct jsl_mb_cfg *variant_memcfg_config(void)
+{
+ return &baseboard_memcfg_cfg;
+}
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