Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.

Felix Singer has uploaded this change for review.

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soc/intel/tigerlake: Hook up SmbusEnable option to devicetree

Hook up SmbusEnable FSP option to devicetree and drop the `SmbusEnable`
setting.

Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 1 insertion(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/59883/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f0858db..e729e8c 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -272,9 +272,6 @@
 	/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
 	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
 
-	/* SMBus */
-	uint8_t SmbusEnable;
-
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 40683e2..24b8575 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -130,7 +130,7 @@
 	/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
 	m_cfg->ChHashMask = 0x30CC;
 	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
+	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
 

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