Subrata Banik has uploaded this change for review.

View Change

soc/intel/icelake: Make use of PCH_DEV_SLOT_ESPI macro

Change-Id: I3be530072a6981760e9fe31e43741b4b480d045e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/icelake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34286/1

diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 420c427..dd87617 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -38,7 +38,7 @@
 	m_cfg->SkipMbpHob = 1;
 
 	/* If Audio Codec is enabled, enable FSP UPD */
-	dev = pcidev_on_root(0x1f, 3);
+	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 3);
 	if (!dev)
 		m_cfg->PchHdaEnable = 0;
 	else

To view, visit change 34286. To unsubscribe, or for help writing mail filters, visit settings.