Patch set 4:Code-Review +2

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1 comment:

• File src/soc/intel/baytrail/romstage/raminit.c:

  • Patch Set #4, Line 170:

    if (mp->mainboard.spd_addrs[i]) {
    				i2c_eeprom_read(mp->mainboard.spd_addrs[i],
    					0, SPD_SIZE, spd_buf[i]);
    				/* NOTE: the MRC expects both SPD pointers
    					to match */
    				mp->mainboard.dram_data[i] = spd_buf;
    			}
    

    (The 0xF0 and 0xF1 are fake SPD addresses the MRC's main function sets as markers for in memory SPD […]

    Actually, the data buffers can be different, but the data for channel 0 needs to be at index 0, and the data for channel 1 needs to be at index 1. Using the same buffer avoids wasting space. I was given this snippet when I had problems getting the MRC to accept my SPDs: https://gist.github.com/Th3Fanbus/e01265a1f1c5b75360edb6c92b5ceeaa

    I can try if different DIMMs and CH1-only setups work on Q1900M. I had quite a bit of trouble making RAM work because Baytrail MRC.bin does not like UDIMMs (I had to patch the SPDs to pretend they're SO-DIMMs) and requires 1.35V operation (I had to patch that too). Now that I put all the pieces together, it retrieves the SPDs from SMBus reliably.

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