Piotr Kleinschmidt has uploaded this change for review.
mb/pcengines/apu2/mptable.c: fix invalid MP table and IRQ table
MP Table and IRQ routing tables were buggy, which results in
Linux kernel panic when 'acpi=noirq' flag was added during boot.
TEST=boot Linux debian 4.19.0-9 on PC Engines apu4 platform
and see if IRQs are correctly assigned to devices analyzing
'cat proc/interrupts' and `lspci -v` outputs.
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: I9eadba65eb5f8f66d1d28c89c7c29d0745c93119
---
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/mptable.c
M src/northbridge/amd/pi/00730F01/pci_devs.h
3 files changed, 34 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42097/1
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 170c912..43a27ea 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -70,7 +70,7 @@
[0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* USB Devs 18/19/20/22 INTA-C */
- [0x30] = 0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,
+ [0x30] = 0x1F,0x12,0x1F,0x12,0x1F,0x12,0x1F,0x00,
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* SATA */
[0x40] = 0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -92,22 +92,22 @@
*/
static const struct pirq_struct mainboard_pirq_data[] = {
/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
+ {IOMMU_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* IOMMU: 00.2 */
{GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */
- {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */
- {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */
+ {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.1 */
+ {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* NIC: 02.2 */
{NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */
+ {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* NIC: 02.4 */
+ {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe slot 1: 02.5 */
{XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */
- {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
- {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
- {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
- {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
- {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
- {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
- {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
- {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
- {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */
- {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */
+ {SATA_DEVFN, {PIRQ_D, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
+ {EHCI1_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI0: 12.0 */
+ {EHCI2_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 13.0 */
+ {SMBUS_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
+ {LPC_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* LPC: 14.3 */
+ {SD_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */
+ {EHCI3_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 16.0 (same device as xHCI 10.1) */
};
/* PIRQ Setup */
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index 8cfec5d..cca3cc7 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -54,6 +54,8 @@
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
+ ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
@@ -62,40 +64,31 @@
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+ /* IOMMU */
+ //ioapic_id = (io_apic_read((u8 *)IO_APIC2_ADDR, 0x00) >> 24);
+ PCI_INT(0x0, 0x0, 0x2, 0x10);
/* SMBUS / ACPI */
PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
/* SD card */
- PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
+ PCI_INT(0x0, 0x14, 0x7, intr_data_ptr[PIRQ_SD]);
/* USB */
- PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
- PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
- PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
- PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
- PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
- PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
- PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_EHCI1]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_EHCI2]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_EHCI3]);
+ PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_EHCI3]);
/* SATA */
PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
/* on board NIC & Slot PCIE */
- PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
- PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-
- /* GPP0 */
- PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
- /* GPP1 */
- PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
- /* GPP2 */
- PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
- /* GPP3 */
- PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
- /* GPP4 */
- PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
+ PCI_INT(0x1, 0x0, 0x0, 0x10);
+ PCI_INT(0x2, 0x0, 0x0, 0x11);
+ PCI_INT(0x3, 0x0, 0x0, 0x12);
+ PCI_INT(0x4, 0x0, 0x0, 0x13);
+ PCI_INT(0x5, 0x0, 0x0, 0x10);
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
diff --git a/src/northbridge/amd/pi/00730F01/pci_devs.h b/src/northbridge/amd/pi/00730F01/pci_devs.h
index 888e54c..91f7274 100644
--- a/src/northbridge/amd/pi/00730F01/pci_devs.h
+++ b/src/northbridge/amd/pi/00730F01/pci_devs.h
@@ -5,6 +5,12 @@
#define BUS0 0
+/* IOMMU */
+#define IOMMU_DEV 0x00
+#define IOMMU_FUNC 2
+#define IOMMU_DEVID 0x1567
+#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV,IOMMU_FUNC)
+
/* Graphics and Display */
#define GFX_DEV 0x1
#define GFX_FUNC 0
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