Elyes Haouas has uploaded this change for review.
sb/intel/bd82x6x: Use {read,write}32p
While on it, sort includes.
Change-Id: Iacc858fbad89b54b1f5891c18cd3043b3963d53f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
2 files changed, 29 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/70292/1
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 28337f6..bf03b1a 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -1,20 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h>
#include <arch/io.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
#include <commonlib/region.h>
-#include <device/pci_def.h>
-#include <cpu/x86/smm.h>
+#include <console/console.h>
#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <cpu/x86/smm.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/me.h>
-#include <southbridge/intel/common/gpio.h>
-#include <cpu/intel/model_206ax/model_206ax.h>
-#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/finalize.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmutil.h>
+#include <types.h>
#include "pch.h"
@@ -168,7 +169,7 @@
/* Steps 3 to 6: If USB3 PORTSC current connect status (bit 0) is set, do IOBP magic */
for (unsigned int port = 0; port < 4; port++) {
- if (read32((void *)(xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0))
+ if (read32p((xhci_bar + XHCI_PORTSC_x_USB3(port))) & (1 << 0))
pch_iobp_update(0xec000082 + 0x100 * port, ~0, 3 << 2);
}
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 3661aba..1cb260a 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -2,12 +2,13 @@
#include <console/console.h>
#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "pch.h"
-#include <device/pci_ehci.h>
#include <device/mmio.h>
+#include <device/pci_ehci.h>
+#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <device/pci.h>
+
+#include "pch.h"
static void usb_ehci_init(struct device *dev)
{
@@ -46,8 +47,8 @@
res = probe_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
/* Number of ports and companion controllers. */
- reg32 = read32((void *)(uintptr_t)(res->base + 4));
- write32((void *)(uintptr_t)(res->base + 4),
+ reg32 = read32p((uintptr_t)(res->base + 4));
+ write32p((uintptr_t)(res->base + 4),
(reg32 & 0xfff00000) | 3);
}
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