Felix Held submitted this change.

View Change


Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 s

The currently used panel type could work with 500 ms but increasing
the value to 1 second allows to use a wider range of LVDS LCD panels,
as many of them specify the delay of 1 s as minimum.

BUG=none
TEST=Test link stability using a panel with minimum re-power delay of
1 s.

Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
index 316eb71..965f62d 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c
@@ -82,8 +82,8 @@
cfg->t2_delay = 0x01;
/* LVDS to backlight active delay: 200 ms */
cfg->t3_timing = 0x04;
- /* Minimum re-power delay: 500 ms */
- cfg->t12_timing = 0x0a;
+ /* Minimum re-power delay: 1 s */
+ cfg->t12_timing = 0x14;
/* Backlight off to LVDS inactive delay: 200 ms */
cfg->t4_timing = 0x04;
/* Enable LVDS to VDD inactive delay. */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b
Gerrit-Change-Number: 72804
Gerrit-PatchSet: 2
Gerrit-Owner: Jan Samek <jan.samek@siemens.com>
Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de>
Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: merged