Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76831?usp=email )
Change subject: mb/google/rex/var/screebo: Enable RTD3 for SSD ......................................................................
mb/google/rex/var/screebo: Enable RTD3 for SSD
Currently, S0iX test is failing because S0i2 susbstate is blocked. Enable RTD3 for SSD to unblock S0i2.2 substate residency.
BUG=none TEST=Screebo can enter into S0iX.
S0iX substate residency w/o this CL - ``` Substate Residency S0i2.0 0 S0i2.1 38451594 S0i2.2 0 ```
S0iX substate residency w/ this CL - ``` Substate Residency S0i2.0 0 S0i2.1 12108 S0i2.2 33878424 ```
Signed-off-by: Kapil Porwal kapilporwal@google.com Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 4567d5d..a7b7d54 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -231,6 +231,13 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "4" + device generic 0 on end + end end # PCIE4_P9 SSD card device ref pcie_rp10 on # Enable SD Card PCIE4 rp10 using clk 7