Shelley Chen has uploaded this change for review.
mb/google/brox: Fix DDR6 DQS config
This was discovered to be incorrect to what was in the schematics.
Correcting this mistake.
BUG=b:311450057,b:300690448
BRANCH=None
TEST=tested on device and it passed memory training
Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043
Signed-off-by: Shelley Chen <shchen@google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/memory.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/79843/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/memory.c b/src/mainboard/google/brox/variants/baseboard/brox/memory.c
index 4b03e21..05434b1 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/memory.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/memory.c
@@ -53,7 +53,7 @@
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
- .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
},
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