Sumeet R Pawnikar has uploaded this change for review.
soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU
Set power limits in devicetree for Tiger Lake Y-SKU varaints.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/systemagent.c
3 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43607/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index e0d3bea..6fdd7fc 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -221,6 +221,16 @@
.tdp_pl2_override = 38,
.tdp_pl4 = 71,
}"
+ register "power_limits_config[POWER_LIMITS_Y_4_CORE]" = "{
+ .tdp_pl1_override = 9,
+ .tdp_pl2_override = 40,
+ .tdp_pl4 = 83,
+ }"
+ register "power_limits_config[POWER_LIMITS_Y_2_CORE]" = "{
+ .tdp_pl1_override = 9,
+ .tdp_pl2_override = 35,
+ .tdp_pl4 = 66,
+ }"
register "Device4Enable" = "1"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 59dab58..403ad69 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -25,7 +25,9 @@
/* The first two are for TGL-U */
#define POWER_LIMITS_U_4_CORE 0
#define POWER_LIMITS_U_2_CORE 1
-#define POWER_LIMITS_MAX 2
+#define POWER_LIMITS_Y_4_CORE 2
+#define POWER_LIMITS_Y_2_CORE 3
+#define POWER_LIMITS_MAX 4
/*
* Enable External V1P05 Rail in: BIT0:S0i1/S0i2,
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index 7b99ef1..f1356e2 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -84,6 +84,12 @@
case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2:
soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
break;
+ case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
+ soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
+ break;
+ case PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2:
+ soc_config = &config->power_limits_config[POWER_LIMITS_Y_2_CORE];
+ break;
default:
printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
"configuration\n", sa_pci_id);
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