Aaron Durbin uploaded patch set #2 to this change.

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soc/amd/picasso: establish full early caching memory map

The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:

Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.

BUG=b:155426691

Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
---
M src/soc/amd/picasso/bootblock/bootblock.c
1 file changed, 59 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42103/2

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