[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Update comments

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/21563

Change subject: nb/intel/i945: Update comments
......................................................................

nb/intel/i945: Update comments

i945M supports two DIMMs, however
i945G* supports four DIMMs and have
their SPD at 0x50/0x51/0x52/0x53.

Change-Id: If4c7aa4723c0a9715e2931e40a041bfcfd55b8b6
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21563/1

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index f10f108..14960b8 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -324,7 +324,7 @@
    int i;

/**
-	 * i945 supports two DIMMs, in two configurations:
+	 * i945M supports two DIMMs, in two configurations:
     *
     * - single channel with two DIMMs
     * - dual channel with one DIMM per channel
@@ -332,6 +332,8 @@
     * In practice dual channel mainboards have their SPD at 0x50/0x52
     * whereas single channel configurations have their SPD at 0x50/0x51.
     *
+	 * i945G* supports four DIMMs, and have their SPD at 0x50/0x51/0x52/0x53.
+	 *
     * The capability register knows a lot about the channel configuration
     * but for now we stick with the information we gather via SPD.
     */