Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jérémy Compostella, Tim Chu.
Patrick Rudolph has uploaded this change for review.
soc/intel/xeon_sp: Drop 1st Gen Xeon-SP
The platform code depends on unreleased binary files and uses
incomplete public header files. In order to reduce maintainance
burden for the Xeon-SP platforms drop this old code.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I12b092f00386cb71fac02d8d0b10375d3241abb3
---
M src/arch/x86/smbios.c
M src/soc/intel/xeon_sp/Makefile.inc
D src/soc/intel/xeon_sp/skx/Kconfig
D src/soc/intel/xeon_sp/skx/Makefile.inc
D src/soc/intel/xeon_sp/skx/chip.c
D src/soc/intel/xeon_sp/skx/chip.h
D src/soc/intel/xeon_sp/skx/cpu.c
D src/soc/intel/xeon_sp/skx/hob_display.c
D src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
D src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h
D src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
D src/soc/intel/xeon_sp/skx/romstage.c
D src/soc/intel/xeon_sp/skx/soc_acpi.c
D src/soc/intel/xeon_sp/skx/soc_smihandler_util.c
D src/soc/intel/xeon_sp/skx/soc_util.c
D src/soc/intel/xeon_sp/skx/upd_display.c
M src/soc/intel/xeon_sp/uncore_acpi.c
17 files changed, 2 insertions(+), 1,413 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80172/1
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index a2038b6..085fe6a 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -56,8 +56,6 @@
return PROCESSOR_UPGRADE_SOCKET_LGA1700;
if (CONFIG(SOC_INTEL_METEORLAKE))
return PROCESSOR_UPGRADE_OTHER;
- if (CONFIG(SOC_INTEL_SKYLAKE_SP))
- return PROCESSOR_UPGRADE_SOCKET_LGA3647_1;
if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
return PROCESSOR_UPGRADE_SOCKET_LGA4189;
if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP))
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index a732c78..4215d0d 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -2,7 +2,6 @@
ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y)
-subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg
subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
deleted file mode 100644
index 5d84387..0000000
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config SOC_INTEL_SKYLAKE_SP
- bool
- select XEON_SP_COMMON_BASE
- select PLATFORM_USES_FSP2_0
- select NO_FSP_TEMP_RAM_EXIT
- help
- Intel Skylake-SP support
-
-if SOC_INTEL_SKYLAKE_SP
-
-config MAINBOARD_USES_FSP2_0
- bool
- default y
-
-config FSP_HEADER_PATH
- string "Location of FSP headers"
- depends on MAINBOARD_USES_FSP2_0
- default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
-
-config MAX_SOCKET
- int
- default 2
-
-# For 2S config, the number of cpus could be as high as
-# 2 threads * 20 cores * 2 sockets
-config MAX_CPUS
- int
- default 80
-
-config PCR_BASE_ADDRESS
- hex
- default 0xfd000000
- help
- This option allows you to select MMIO Base Address of sideband bus.
-
-config DCACHE_RAM_BASE
- hex
- default 0xfe800000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x200000
-
-config DCACHE_BSP_STACK_SIZE
- hex
- default 0x10000
-
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xfff0fdc0
-
-config CPU_MICROCODE_CBFS_LEN
- hex
- default 0x7C00
-
-config IED_REGION_SIZE
- hex
- default 0x400000
-
-config IFD_CHIPSET
- string
- default "lbg"
-
-config XEON_SP_HAVE_IIO_IOAPIC
- bool
- default y
-
-endif
diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc
deleted file mode 100644
index 0f75eec..0000000
--- a/src/soc/intel/xeon_sp/skx/Makefile.inc
+++ /dev/null
@@ -1,30 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y)
-
-subdirs-y += ../../../../cpu/intel/microcode
-subdirs-y += ../../../../cpu/intel/turbo
-
-postcar-y += soc_util.c
-
-romstage-y += soc_util.c
-romstage-y += romstage.c
-romstage-y += soc_util.c
-romstage-y += hob_display.c
-romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-
-ramstage-y += soc_acpi.c
-ramstage-y += chip.c
-ramstage-y += soc_util.c
-ramstage-y += cpu.c
-ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
-ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += hob_display.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c
-
-CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
-
-cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04
-
-endif ## CONFIG_SOC_INTEL_SKYLAKE_SP
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
deleted file mode 100644
index b468842..0000000
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <cbfs.h>
-#include <console/console.h>
-#include <device/pci.h>
-#include <gpio.h>
-#include <intelblocks/acpi.h>
-#include <soc/acpi.h>
-#include <soc/chip_common.h>
-#include <soc/pch.h>
-#include <soc/soc_pch.h>
-#include <soc/ramstage.h>
-#include <soc/soc_util.h>
-#include <soc/util.h>
-
-#if CONFIG(HAVE_ACPI_TABLES)
-const char *soc_acpi_name(const struct device *dev)
-{
- if (dev->path.type == DEVICE_PATH_DOMAIN)
- return "PC00";
- return NULL;
-}
-#endif
-
-static struct device_operations pci_domain_ops = {
- .read_resources = iio_pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .scan_bus = iio_pci_domain_scan_bus,
-#if CONFIG(HAVE_ACPI_TABLES)
- .write_acpi_tables = &northbridge_write_acpi_tables,
- .acpi_name = soc_acpi_name
-#endif
-};
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = noop_read_resources,
- .set_resources = noop_set_resources,
- .init = mp_cpu_bus_init,
-#if CONFIG(HAVE_ACPI_TABLES)
- /* defined in src/soc/intel/common/block/acpi/acpi.c */
- .acpi_fill_ssdt = generate_cpu_entries,
-#endif
-};
-
-static void soc_enable_dev(struct device *dev)
-{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- attach_iio_stacks(dev);
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- } else if (dev->path.type == DEVICE_PATH_GPIO) {
- block_gpio_enable(dev);
- }
-}
-
-static void soc_init(void *data)
-{
- printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
- fsp_silicon_init();
- override_hpet_ioapic_bdf();
- pch_lock_dmictl();
-}
-
-static void soc_final(void *data)
-{
- // Temp Fix - should be done by FSP, in 2S bios completion
- // is not carried out on socket 2
- set_bios_init_completion();
-}
-
-void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
-{
- const struct microcode *microcode_file;
- size_t microcode_len;
-
- microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len);
-
- if ((microcode_file) && (microcode_len != 0)) {
- /* Update CPU Microcode patch base address/size */
- silupd->FspsConfig.PcdCpuMicrocodePatchBase =
- (uint32_t)microcode_file;
- silupd->FspsConfig.PcdCpuMicrocodePatchSize =
- (uint32_t)microcode_len;
- }
-
- mainboard_silicon_init_params(silupd);
-}
-
-struct chip_operations soc_intel_xeon_sp_skx_ops = {
- CHIP_NAME("Intel Skylake-SP")
- .enable_dev = soc_enable_dev,
- .init = soc_init,
- .final = soc_final
-};
-
-struct pci_operations soc_pci_ops = {
- .set_subsystem = pci_dev_set_subsystem,
-};
diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h
deleted file mode 100644
index 0c05211..0000000
--- a/src/soc/intel/xeon_sp/skx/chip.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _SOC_CHIP_H_
-#define _SOC_CHIP_H_
-
-#include <gpio.h>
-#include <intelblocks/cfg.h>
-#include <soc/acpi.h>
-#include <soc/irq.h>
-#include <stdint.h>
-
-struct soc_intel_xeon_sp_skx_config {
- /* Common struct containing soc config data required by common code */
- struct soc_intel_common_config common_soc_config;
-
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- /**
- * Device Interrupt Routing configuration
- * Interrupt Pin x Route.
- * 0h = PIRQA#
- * 1h = PIRQB#
- * 2h = PIRQC#
- * 3h = PIRQD#
- * 4h = PIRQE#
- * 5h = PIRQF#
- * 6h = PIRQG#
- * 7h = PIRQH#
- */
-
- uint16_t ir00_routing;
- uint16_t ir01_routing;
- uint16_t ir02_routing;
- uint16_t ir03_routing;
- uint16_t ir04_routing;
-
- /**
- * Device Interrupt Polarity Control
- * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
- * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
- * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
- * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
- */
- uint32_t ipc0;
- uint32_t ipc1;
- uint32_t ipc2;
- uint32_t ipc3;
-
- uint64_t turbo_ratio_limit;
- uint64_t turbo_ratio_limit_cores;
-
- uint32_t pstate_req_ratio;
-
- uint32_t vtd_support;
- uint32_t coherency_support;
- uint32_t ats_support;
-
- /* Generic IO decode ranges */
- uint32_t gen1_dec;
- uint32_t gen2_dec;
- uint32_t gen3_dec;
- uint32_t gen4_dec;
-
- /* TCC activation offset */
- uint32_t tcc_offset;
-
- enum acpi_cstate_mode cstate_states;
-};
-
-typedef struct soc_intel_xeon_sp_skx_config config_t;
-
-#endif
diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
deleted file mode 100644
index 009527c..0000000
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <console/console.h>
-#include <console/debug.h>
-#include <intelblocks/cpulib.h>
-#include <cpu/cpu.h>
-#include <cpu/intel/cpu_ids.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/mp.h>
-#include <cpu/intel/turbo.h>
-#include <soc/msr.h>
-#include <soc/soc_util.h>
-#include <soc/smmrelocate.h>
-#include <soc/util.h>
-#include <assert.h>
-#include "chip.h"
-#include <cpu/intel/smm_reloc.h>
-#include <cpu/intel/em64t101_save_state.h>
-#include <types.h>
-
-static const config_t *chip_config = NULL;
-
-bool cpu_soc_is_in_untrusted_mode(void)
-{
- /* IA_UNTRUSTED_MODE is not supported in Skylake */
- return false;
-}
-
-void cpu_soc_bios_done(void)
-{
- /* IA_UNTRUSTED_MODE is not supported in Skylake */
-}
-
-static void xeon_configure_mca(void)
-{
- msr_t msr;
- struct cpuid_result cpuid_regs;
-
- /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE
- * and CPUID.(EAX=1):EDX[14]==1 MCA*/
- cpuid_regs = cpuid(1);
- if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14))
- return;
-
- msr = rdmsr(IA32_MCG_CAP);
- if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) {
- /* Enable all error logging */
- msr.lo = msr.hi = 0xffffffff;
- wrmsr(IA32_MCG_CTL, msr);
- }
-
- /* TODO(adurbin): This should only be done on a cold boot. Also, some
- of these banks are core vs package scope. For now every CPU clears
- every bank. */
- mca_configure();
-}
-
-static void xeon_sp_core_init(struct device *cpu)
-{
- msr_t msr;
-
- printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n",
- __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id,
- cpu->path.apic.package_id);
- assert(chip_config);
-
- /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/
- msr.hi = 0;
- msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE);
- wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
-
- /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */
- msr = rdmsr(MSR_POWER_CTL);
- msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE
- | PROCHOT_LOCK_ENABLE);
- wrmsr(MSR_POWER_CTL, msr);
-
- /* Set P-State ratio */
- msr = rdmsr(MSR_IA32_PERF_CTRL);
- msr.lo &= ~PSTATE_REQ_MASK;
- msr.lo |= (chip_config->pstate_req_ratio << PSTATE_REQ_SHIFT);
- wrmsr(MSR_IA32_PERF_CTRL, msr);
-
- /*
- * Set HWP base feature, EPP reg enumeration, lock thermal and msr
- * TODO: Set LOCK_MISC_PWR_MGMT_MSR, Unexpected Exception if you
- * lock & issue wrmsr on every thread
- * This is package level MSR. Need to check if it updates correctly on
- * multi-socket platform.
- */
- msr = rdmsr(MSR_MISC_PWR_MGMT);
- if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */
- msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR |
- LOCK_THERM_INT);
- wrmsr(MSR_MISC_PWR_MGMT, msr);
- }
-
- /* TODO MSR_VR_MISC_CONFIG */
-
- /* Set current limit lock */
- msr = rdmsr(MSR_VR_CURRENT_CONFIG);
- msr.lo |= CURRENT_LIMIT_LOCK;
- wrmsr(MSR_VR_CURRENT_CONFIG, msr);
-
- /* Set Turbo Ratio Limits */
- msr.lo = chip_config->turbo_ratio_limit & 0xffffffff;
- msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff;
- wrmsr(MSR_TURBO_RATIO_LIMIT, msr);
-
- /* Set Turbo Ratio Limit Cores */
- msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff;
- msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff;
- wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr);
-
- /* set Turbo Activation ratio */
- msr.hi = 0;
- msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
- msr.lo |= MAX_NON_TURBO_RATIO;
- wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
-
- /* Enable Fast Strings */
- msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= FAST_STRINGS_ENABLE_BIT;
- wrmsr(IA32_MISC_ENABLE, msr);
-
- /* Set energy policy */
- msr_t msr1 = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG);
- msr.lo = (msr1.lo & EPB_ENERGY_POLICY_MASK) >> EPB_ENERGY_POLICY_SHIFT;
- msr.hi = 0;
- wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr);
-
- /* Enable Turbo */
- enable_turbo();
-
- /* Enable speed step. */
- if (get_turbo_state() == TURBO_ENABLED) {
- msr = rdmsr(IA32_MISC_ENABLE);
- msr.lo |= SPEED_STEP_ENABLE_BIT;
- wrmsr(IA32_MISC_ENABLE, msr);
- }
-
- /* Clear out pending MCEs */
- xeon_configure_mca();
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = xeon_sp_core_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- /* Skylake-SP A0/A1 CPUID 0x506f0*/
- {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1, CPUID_EXACT_MATCH_MASK },
- /* Skylake-SP B0 CPUID 0x506f1*/
- {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0, CPUID_EXACT_MATCH_MASK },
- /* Skylake-SP 4 CPUID 0x50654*/
- {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4, CPUID_EXACT_MATCH_MASK },
- CPU_TABLE_END
-};
-
-static const struct cpu_driver driver __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
-
-#define CPU_BCLK 100
-
-static void set_max_turbo_freq(void)
-{
- msr_t msr, perf_ctl;
-
- FUNC_ENTER();
- perf_ctl.hi = 0;
-
- /* Check for configurable TDP option */
- if (get_turbo_state() == TURBO_ENABLED) {
- msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else if (cpu_config_tdp_levels()) {
- /* Set to nominal TDP ratio */
- msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
- perf_ctl.lo = (msr.lo & 0xff) << 8;
- } else {
- /* Platform Info bits 15:8 give max ratio */
- msr = rdmsr(MSR_PLATFORM_INFO);
- perf_ctl.lo = msr.lo & 0xff00;
- }
- wrmsr(IA32_PERF_CTL, perf_ctl);
-
- printk(BIOS_DEBUG, "cpu: frequency set to %d\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
- FUNC_EXIT();
-}
-
-/*
- * Do essential initialization tasks before APs can be fired up
- *
- * Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
- * creates the MTRR solution that the APs will use. Otherwise APs will try to
- * apply the incomplete solution as the BSP is calculating it.
- */
-static void pre_mp_init(void)
-{
- printk(BIOS_DEBUG, "%s: entry\n", __func__);
-
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-}
-
-static void post_mp_init(void)
-{
- /* Set Max Ratio */
- set_max_turbo_freq();
-
- if (CONFIG(HAVE_SMI_HANDLER))
- global_smi_enable();
-}
-
-/*
- * CPU initialization recipe
- *
- * Note that no microcode update is passed to the init function. CSE updates
- * the microcode on all cores before releasing them from reset. That means that
- * the BSP and all APs will come up with the same microcode revision.
- */
-static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_platform_thread_count,
- .get_smm_info = get_smm_info,
- .pre_mp_smm_init = smm_southbridge_clear_state,
- .relocation_handler = smm_relocation_handler,
- .post_mp_init = post_mp_init,
-};
-
-void mp_init_cpus(struct bus *bus)
-{
- FUNC_ENTER();
-
- /*
- * This gets used in cpu device callback. Other than cpu 0,
- * rest of the CPU devices do not have
- * chip_info updated. Global chip_config is used as workaround
- */
- chip_config = bus->dev->chip_info;
-
- config_reset_cpl3_csrs();
-
- /* calls src/cpu/x86/mp_init.c */
- /* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(bus, &mp_ops);
-
- FUNC_EXIT();
-}
diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c
deleted file mode 100644
index bc65e64..0000000
--- a/src/soc/intel/xeon_sp/skx/hob_display.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-#include <assert.h>
-#include <hob_iiouds.h>
-#include <hob_memmap.h>
-
-static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
-static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
-
-struct guid_name_map {
- const void *guid;
- const char *name;
-};
-
-static const struct guid_name_map guid_names[] = {
- { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" },
- { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" },
-};
-
-const char *soc_get_guid_name(const uint8_t *guid)
-{
- size_t index;
-
- /* Compare the GUID values in this module */
- for (index = 0; index < ARRAY_SIZE(guid_names); index++)
- if (fsp_guid_compare(guid, guid_names[index].guid))
- return guid_names[index].name;
-
- return NULL;
-}
-
-void soc_display_hob(const struct hob_header *hob)
-{
- const struct hob_resource *res;
-
- res = fsp_hob_header_to_resource(hob);
- assert(res);
- printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n",
- res->type, res->attribute_type, res->addr, res->length);
- printk(BIOS_DEBUG, "\tOwner GUID: ");
- fsp_print_guid(BIOS_DEBUG, res->owner_guid);
- printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid));
-
- if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0)
- soc_display_iio_universal_data_hob();
- else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0)
- soc_display_memmap_hob();
- else
- hexdump(hob, hob->length);
-}
-
-void soc_display_memmap_hob(void)
-{
- size_t hob_size = 0;
- const struct SystemMemoryMapHob *hob =
- fsp_find_extension_hob_by_guid(fsp_hob_memmap_guid, &hob_size);
- assert(hob && hob_size != 0);
-
- printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n");
- printk(BIOS_DEBUG, "hob: %p, hob_size: 0x%zx, SystemMemoryMapHob size: 0x%zx, "
- "MAX_SOCKET: %d, SAD_RULES: %d\n",
- hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES);
- printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, "
- "highMemSize: 0x%x\n",
- hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize);
- printk(BIOS_DEBUG, "\tasilLoMemBase: 0x%x, asilHiMemBase: 0x%x, asilLoMemSize: 0x%x, "
- "asilHiMemSize: 0x%x\n",
- hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize);
- printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x, memMode: 0x%x, volMemMode: 0x%x, "
- "DimmType: 0x%x, DramType: 0x%x\n",
- hob->memSize, hob->memFreq, hob->memMode, hob->volMemMode,
- hob->DimmType, hob->DramType);
- printk(BIOS_DEBUG, "\tNumChPerMC: 0x%x, numberEntries: 0x%x, maxIMC: 0x%x, maxCh: 0x%x\n",
- hob->NumChPerMC, hob->numberEntries, hob->maxIMC, hob->maxCh);
-
- printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries);
- for (int e = 0; e < hob->numberEntries; ++e) {
- const struct SystemMemoryMapElement *mem_element = &hob->Element[e];
- printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n",
- e, mem_element->BaseAddress,
- mem_element->ElementSize, mem_element->Type);
- }
-}
-
-void soc_display_iio_universal_data_hob(void)
-{
- size_t hob_size = 0;
- const IIO_UDS *hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_uds_guid, &hob_size);
-
- assert(hob && hob_size != 0);
-
- printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n");
-
- printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n");
- printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType);
- printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType);
- printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType);
- printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus);
- for (int x = 0; x < MAX_SOCKET; ++x) {
- printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, "
- "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n",
- x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x],
- hob->SystemStatus.MaxCoreToBusRatio[x],
- hob->SystemStatus.MinCoreToBusRatio[x]);
- }
- printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n",
- hob->SystemStatus.CurrentCoreToBusRatio);
- printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n",
- hob->SystemStatus.IntelSpeedSelectCapable);
- printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n",
- hob->SystemStatus.IssConfigTdpLevelInfo);
- for (int x = 0; x < TDP_MAX_LEVEL; ++x) {
- printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, "
- "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n",
- x, hob->SystemStatus.IssConfigTdpTdpInfo[x],
- hob->SystemStatus.IssConfigTdpPowerInfo[x],
- hob->SystemStatus.IssConfigTdpCoreCount[x]);
- }
- printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n",
- hob->SystemStatus.socketPresentBitMap);
- printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit);
- printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit);
- printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase);
- printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC);
- printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh);
- printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC);
-
- printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
- printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
- printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
- hob->PlatformData.PlatGlobalMmiolBase);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
- hob->PlatformData.PlatGlobalMmiolLimit);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
- hob->PlatformData.PlatGlobalMmiohBase);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
- hob->PlatformData.PlatGlobalMmiohLimit);
- printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
- printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
- printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
- printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize);
- printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm);
- printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO);
- printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber);
- printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity);
- printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity);
- printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n",
- hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo);
-
- for (int s = 0; s < MAX_SOCKET; ++s) {
- printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s);
- printk(BIOS_DEBUG, "\tSocketID: 0x%x\n",
- hob->PlatformData.IIO_resource[s].SocketID);
- printk(BIOS_DEBUG, "\tBusBase: 0x%x\n",
- hob->PlatformData.IIO_resource[s].BusBase);
- printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n",
- hob->PlatformData.IIO_resource[s].BusLimit);
- printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceIoBase);
- printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceIoLimit);
- printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n",
- hob->PlatformData.IIO_resource[s].IoApicBase);
- printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
- hob->PlatformData.IIO_resource[s].IoApicLimit);
- printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem32Base);
- printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem32Limit);
- printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem64Base);
- printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem64Limit);
-
- printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
- for (int x = 0; x < MAX_IIO_STACK; ++x) {
- const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
- printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x);
- printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
- printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
- printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
- ri->PciResourceIoBase);
- printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
- ri->PciResourceIoLimit);
- printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
- printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
- printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
- ri->PciResourceMem32Base);
- printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",
- ri->PciResourceMem32Limit);
- printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n",
- ri->PciResourceMem64Base);
- printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n",
- ri->PciResourceMem64Limit);
- printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress);
- }
-
- printk(BIOS_DEBUG, "\t============ PcieInfo ================\n");
- IIO_RESOURCE_INSTANCE iio_resource =
- hob->PlatformData.IIO_resource[s];
- for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
- printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n",
- p, iio_resource.PcieInfo.PortInfo[p].Device,
- iio_resource.PcieInfo.PortInfo[p].Function);
- }
- }
-
- printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n");
- for (int socket = 0; socket < MAX_SOCKET; ++socket) {
- for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
- printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n",
- socket, stack,
- hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]);
- }
- }
-}
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
deleted file mode 100644
index 3d518fa..0000000
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _SOC_PCI_DEVS_H_
-#define _SOC_PCI_DEVS_H_
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <hob_iiouds.h>
-#include <soc/pch_pci_devs.h>
-
-#define dump_csr(fmt, dev, reg) \
- printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
- fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
- ((uint32_t)dev >> 12) & 0x07, \
- #reg, reg, pci_s_read_config32(dev, reg))
-
-#define dump_csr64(fmt, dev, reg) \
- printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \
- fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
- ((uint32_t)dev >> 12) & 0x07, #reg, reg, \
- pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg))
-
-#define SAD_ALL_DEV 29
-#define SAD_ALL_FUNC 0
-#define SAD_ALL_PAM0123_CSR 0x40
-#define PAM_LOCK BIT(0)
-#define SAD_ALL_PAM456_CSR 0x44
-
-#if !defined(__SIMPLE_DEVICE__)
-#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func))
-#else
-#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func)
-#endif
-
-#define PCU_IIO_STACK 1
-#define PCU_DEV 30
-#define PCU_CR1_FUN 1
-
-#define PCU_CR0_FUN 0
-#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN)
-#define PCU_CR0_PLATFORM_INFO 0xa8
-#define PCU_CR0_P_STATE_LIMITS 0xd8
-#define P_STATE_LIMITS_LOCK_SHIFT 31
-#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT)
-#define PCU_CR0_TEMPERATURE_TARGET 0xe4
-#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8
-#define PCU_CR0_CURRENT_CONFIG 0xf8
-#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */
-#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT)
-#define PCU_CR0_PMAX 0xf0
-#define PMAX_LOCK BIT(31)
-
-#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
-
-#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90
-#define BIOS_MB_RUN_BUSY_MASK BIT(31)
-#define BIOS_MB_CMD_MASK 0xff
-#define BIOS_CMD_READ_PCU_MISC_CFG 0x5
-#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6
-#define BIOS_ERR_INVALID_CMD 0x01
-
-#define PCU_CR1_BIOS_RESET_CPL_REG 0x94
-#define RST_CPL1_MASK BIT(1)
-#define RST_CPL2_MASK BIT(2)
-#define RST_CPL3_MASK BIT(3)
-#define RST_CPL4_MASK BIT(4)
-#define PCODE_INIT_DONE1_MASK BIT(9)
-#define PCODE_INIT_DONE2_MASK BIT(10)
-#define PCODE_INIT_DONE3_MASK BIT(11)
-#define PCODE_INIT_DONE4_MASK BIT(12)
-
-#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0
-#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
-
-#if !defined(__SIMPLE_DEVICE__)
-#define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__)
-#else
-#define _UBOX_DEV(func) PCI_DEV(0, UBOX_DEV, func)
-#endif
-
-#define UBOX_DEV 8
-
-#define UBOX_PMON_BUS 0
-#define UBOX_PMON_DEV 8
-#define UBOX_PMON_FUNC 1
-#define UBOX_DEV_PMON _UBOX_DEV(UBOX_PMON_FUNC)
-#define SMM_FEATURE_CONTROL 0x7c
-#define SMM_CODE_CHK_EN BIT(2)
-#define SMM_FEATURE_CONTROL_LOCK BIT(0)
-
-#define UBOX_DECS_BUS 0
-#define UBOX_DECS_DEV 8
-#define UBOX_DECS_FUNC 2
-#define UBOX_DECS_CPUBUSNO_CSR 0xcc
-#define UBOX_DECS_CPUBUSNO1_CSR 0xd0
-
-#define VTD_TOLM_CSR 0xd0
-#define VTD_TSEG_BASE_CSR 0xa8
-#define VTD_TSEG_LIMIT_CSR 0xac
-#define VTD_EXT_CAP_LOW 0x10
-#define VTD_MMCFG_BASE_CSR 0x90
-#define VTD_MMCFG_LIMIT_CSR 0x98
-#define VTD_TOHM_CSR 0xd4
-#define VTD_MMIOL_CSR 0xdc
-#define VTD_ME_BASE_CSR 0xf0
-#define VTD_ME_LIMIT_CSR 0xf8
-#define VTD_VERSION 0x00
-#define VTD_CAP 0x08
-#define VTD_CAP_LOW 0x08
-#define VTD_CAP_HIGH 0x0C
-#define VTD_EXT_CAP_HIGH 0x14
-#define VTD_LTDPR 0x290
-
-#define PCU_CR1_C2C3TT_REG 0xdc
-#define PCU_CR1_PCIE_ILTR_OVRD 0xfc
-#define PCU_CR1_SAPMCTL 0xb0
-#define SAPMCTL_LOCK_SHIFT 31
-#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT)
-#define PCU_CR1_MC_BIOS_REQ 0x98
-
-#define PCU_CR2_FUN 2
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c
-#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90
-#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */
-#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc
-#define UNCORE_PLIMIT_OVERRIDE_BIT 20
-#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT)
-#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0
-#define PROCHOT_RATIO 0xa /* bits 0:7 */
-
-#define CHA_UTIL_ALL_DEV 29
-#define CHA_UTIL_ALL_FUNC 1
-#define CHA_UTIL_ALL_MMCFG_CSR 0xc0
-
-#define MMAP_VTD_CFG_REG_DEVID 0x2024
-#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034
-#define VTD_DEV_NUM 0x5
-#define VTD_FUNC_NUM 0x0
-
-#if !defined(__SIMPLE_DEVICE__)
-#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM))
-#else
-#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
-#endif
-
-#define CBDMA_DEV_NUM 0x04
-#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function
-#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB
-
-#define VMD_DEV_NUM 0x05
-#define VMD_FUNC_NUM 0x05
-
-#define APIC_DEV_NUM 0x05
-#define APIC_FUNC_NUM 0x00
-
-// DMI3 B0D0F0 registers
-#define DMI3_DEVID 0x2020
-#define DMIRCBAR 0x50
-#define ERRINJCON 0x1d8
-
-// IIO DFX Global D7F7 registers
-#define IIO_DFX_TSWCTL0 0x30c
-#define IIO_DFX_LCK_CTL 0x504
-
-pci_devfn_t soc_get_ubox_pmon_dev(void);
-
-#endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h
deleted file mode 100644
index e524cea..0000000
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef _SOC_MSR_SKX_H_
-#define _SOC_MSR_SKX_H_
-
-/* MCA_ERROR_CONTROL */
-#define U2C_SMI_ENABLED (1 << 2)
-
-/* IA32_ERR_CTRL */
-#define CORE_ERR_DISABLE (1 << 5)
-#define CMCI_DISABLE (1 << 4)
-#define UCE_TO_CE_DOWNGRADE (1 << 2)
-
-/* MSR_PKG_CST_CONFIG_CONTROL */
-#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT)
-
-/* MSR_POWER_CTL (SKX and CPX) */
-#define FAST_BRK_SNP_ENABLE_SHIFT 3
-#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT)
-#define FAST_BRK_INT_ENABLE_SHIFT 4
-#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT)
-#define PHOLD_CST_PREVENTION_INIT_SHIFT 6
-#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT)
-#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18
-#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT)
-#define PROCHOT_OUTPUT_DISABLE_SHIFT 21
-#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT)
-#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24
-#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT)
-#define PROCHOT_LOCK_SHIFT 27
-#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT)
-#define LTR_IIO_DISABLE_SHIFT 29
-#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT)
-
-#endif /* _SOC_MSR_SKX_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
deleted file mode 100644
index 379cdc8..0000000
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_UTIL_H_
-#define _SOC_UTIL_H_
-
-#include <hob_iiouds.h>
-#include <hob_memmap.h>
-
-void config_reset_cpl3_csrs(void);
-
-const struct SystemMemoryMapHob *get_system_memory_map(void);
-
-uint8_t get_stack_busno(const uint8_t stack);
-uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
-uint32_t get_socket_ubox_busno(uint32_t socket);
-
-int soc_get_stack_for_port(int port);
-uint8_t get_cxl_node_count(void);
-
-#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c
deleted file mode 100644
index a5c78f6..0000000
--- a/src/soc/intel/xeon_sp/skx/romstage.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/romstage.h>
-#include <intelblocks/rtc.h>
-#include <soc/romstage.h>
-#include <soc/soc_util.h>
-
-#include "chip.h"
-
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
- const config_t *config = config_of_soc();
- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-
- mupd->FspmUpdVersion = FSP_UPD_VERSION;
-
- // ErrorLevel - 0 (disable) to 8 (verbose)
- m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
- m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
-
- mainboard_memory_init_params(mupd);
-
- m_cfg->VTdConfig.VTdSupport = config->vtd_support;
- m_cfg->VTdConfig.CoherencySupport = config->coherency_support;
- m_cfg->VTdConfig.ATS = config->ats_support;
-}
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
deleted file mode 100644
index dfbd878..0000000
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/vga.h>
-#include <assert.h>
-#include <cpu/intel/turbo.h>
-#include <device/mmio.h>
-#include <device/pci.h>
-#include <intelblocks/acpi.h>
-#include <soc/acpi.h>
-#include <soc/iomap.h>
-#include <soc/msr.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <soc/soc_util.h>
-#include <soc/util.h>
-
-int soc_madt_sci_irq_polarity(int sci)
-{
- if (sci >= 20)
- return MP_IRQ_POLARITY_LOW;
- else
- return MP_IRQ_POLARITY_HIGH;
-}
-
-uint32_t soc_read_sci_irq_select(void)
-{
- struct device *dev = PCH_DEV_PMC;
-
- if (!dev)
- return 0;
-
- return pci_read_config32(dev, PMC_ACPI_CNT);
-}
-
-void soc_fill_fadt(acpi_fadt_t *fadt)
-{
- const uint16_t pmbase = ACPI_BASE_ADDRESS;
-
- /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
- fadt->flags &= ~(ACPI_FADT_SEALED_CASE);
- fadt->flags |= ACPI_FADT_SLEEP_TYPE;
-
- fadt->pm2_cnt_blk = pmbase + PM2_CNT;
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
-
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
-
- fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
- /* PM Extended Registers */
- fill_fadt_extended_pm_io(fadt);
-}
-
-void uncore_fill_ssdt(const struct device *device)
-{
- const IIO_UDS *hob = get_iio_uds();
-
- /* Only add RTxx entries once. */
- if (device->bus->secondary != 0)
- return;
-
- for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
- if (!soc_cpu_is_enabled(socket))
- continue;
- iio++;
- IIO_RESOURCE_INSTANCE iio_resource =
- hob->PlatformData.IIO_resource[socket];
- for (int stack = 0; stack <= PSTACK2; ++stack) {
- const STACK_RES *ri = &iio_resource.StackRes[stack];
- char rtname[16];
-
- snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack);
- acpigen_write_scope(rtname);
-
- acpigen_write_name("_CRS");
-
- printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
- rtname, socket, stack);
-
- acpigen_write_resourcetemplate_header();
-
- /* bus resource */
- acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
- 0x0, (ri->BusLimit - ri->BusBase + 1));
-
- // additional io resources on socket 0 bus 0
- if (socket == 0 && stack == 0) {
- /* ACPI 6.4.2.5 I/O Port Descriptor */
- acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
-
- /* IO decode CF8-CFF */
- acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF,
- 0, 0x03B0);
- acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7,
- 0, 0x0918);
- acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB,
- 0, 0x000C);
- acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF,
- 0, 0x0020);
- }
-
- /* IO resource */
- acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
- ri->PciResourceIoLimit, 0x0,
- (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
-
- // additional mem32 resources on socket 0 bus 0
- if (socket == 0 && stack == 0) {
- acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE,
- VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE);
- acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
- (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
- SPI_BASE_SIZE);
- }
-
- /* Mem32 resource */
- acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
- ri->PciResourceMem32Limit, 0x0,
- (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
-
- /* Mem64 resource */
- acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
- ri->PciResourceMem64Limit, 0x0,
- (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
-
- acpigen_write_resourcetemplate_footer();
-
- /* Scope */
- acpigen_pop_len();
- }
- }
-}
-
-void soc_power_states_generation(int core, int cores_per_package)
-{
-}
diff --git a/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c b/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c
deleted file mode 100644
index 6f772cc..0000000
--- a/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/pci_devs.h>
-
-pci_devfn_t soc_get_ubox_pmon_dev(void)
-{
- return UBOX_DEV_PMON;
-}
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
deleted file mode 100644
index a5db8fd..0000000
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <assert.h>
-#include <console/console.h>
-#include <device/pci.h>
-#include <hob_iiouds.h>
-#include <intelblocks/cpulib.h>
-#include <intelblocks/pcr.h>
-#include <soc/iomap.h>
-#include <soc/msr.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/soc_util.h>
-#include <soc/util.h>
-
-
-/*
- * +-------------------------+ TOLM
- * | System Management Mode |
- * | code and data |
- * | (TSEG) |
- * +-------------------------+ SMM base (aligned)
- * | |
- * | Chipset Reserved Memory |
- * | |
- * +-------------------------+ top_of_ram (aligned)
- * | |
- * | CBMEM Root |
- * | |
- * +-------------------------+
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+
- * | |
- * | Various CBMEM Entries |
- * | |
- * +-------------------------+ top_of_stack (8 byte aligned)
- * | |
- * | stack (CBMEM Entry) |
- * | |
- * +-------------------------+
- */
-
-const struct SystemMemoryMapHob *get_system_memory_map(void)
-{
- size_t hob_size;
- const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
- const struct SystemMemoryMapHob *memmap_addr;
-
- memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
- assert(memmap_addr && hob_size != 0);
-
- return memmap_addr;
-}
-
-bool is_pcie_iio_stack_res(const STACK_RES *res)
-{
- return res->BusBase < res->BusLimit;
-}
-
-uint8_t get_stack_busno(const uint8_t stack)
-{
- if (stack >= MAX_IIO_STACK) {
- printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack);
- return 0;
- }
- const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC);
- const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR;
- return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff;
-}
-
-uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
-{
- const IIO_UDS *hob = get_iio_uds();
-
- assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
-
- return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
-}
-
-uint32_t get_socket_ubox_busno(uint32_t socket)
-{
- if (socket == 0)
- return get_stack_busno(PCU_IIO_STACK);
-
- return get_socket_stack_busno(socket, PCU_IIO_STACK);
-}
-
-void config_reset_cpl3_csrs(void)
-{
- uint32_t data, plat_info, max_min_turbo_limit_ratio;
-
- for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
- uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-
- /* configure PCU_CR0_FUN csrs */
- pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
- data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
- data |= P_STATE_LIMITS_LOCK;
- pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
-
- plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
- dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
- max_min_turbo_limit_ratio =
- (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
- MAX_NON_TURBO_LIM_RATIO_SHIFT;
- printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
- plat_info, max_min_turbo_limit_ratio);
-
- /* configure PCU_CR1_FUN csrs */
- pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
- data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
- /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
- data &= 0x0fffffff;
- data |= SAPMCTL_LOCK_MASK;
- pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
-
- /* configure PCU_CR1_FUN csrs */
- pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
-
- data = PCIE_IN_PKGCSTATE_L1_MASK;
- pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
-
- data = KTI_IN_PKGCSTATE_L1_MASK;
- pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
-
- data = PROCHOT_RATIO;
- printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
- pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
- dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
-
- data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
- data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
- pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
- }
-}
-
-/*
- * EX: SKX-SP
- * Ports Stack Stack(HOB) IioConfigIou
- * ==========================================
- * 0 CSTACK stack 0 IOU0
- * 1A..1D PSTACKZ stack 1 IOU1
- * 2A..2D PSTACK1 stack 2 IOU2
- * 3A..3D PSTACK2 stack 3 IOU3
- * 5A..4D PSTACK3 stack 4 IOU4
- * 5A..5D PSTACK4 stack 5 IOU5
- */
-int soc_get_stack_for_port(int port)
-{
- if (port == PORT_0)
- return CSTACK;
- else if (port >= PORT_1A && port <= PORT_1D)
- return PSTACK0;
- else if (port >= PORT_2A && port <= PORT_2D)
- return PSTACK1;
- else if (port >= PORT_3A && port <= PORT_3D)
- return PSTACK2;
- else if (port >= PORT_4A && port <= PORT_4D)
- return PSTACK3; // MCP0
- else if (port >= PORT_5A && port <= PORT_5D)
- return PSTACK4; // MCP1
- else
- return -1;
-}
-
-uint8_t soc_get_iio_ioapicid(int socket, int stack)
-{
- uint8_t ioapic_id = socket ? 0xf : 0x9;
- switch (stack) {
- case CSTACK:
- break;
- case PSTACK0:
- ioapic_id += 1;
- break;
- case PSTACK1:
- ioapic_id += 2;
- break;
- case PSTACK2:
- ioapic_id += 3;
- break;
- default:
- return 0xff;
- }
- return ioapic_id;
-}
diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c
deleted file mode 100644
index c718a58..0000000
--- a/src/soc/intel/xeon_sp/skx/upd_display.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <console/console.h>
-#include <fsp/util.h>
-#include <lib.h>
-
-#define DUMP_UPD(old, new, field) \
- fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
-
-/* Display the UPD parameters for MemoryInit */
-void soc_display_fspm_upd_params(
- const FSPM_UPD *fspm_old_upd,
- const FSPM_UPD *fspm_new_upd)
-{
- const FSP_M_CONFIG *new;
- const FSP_M_CONFIG *old;
-
- old = &fspm_old_upd->FspmConfig;
- new = &fspm_new_upd->FspmConfig;
-
- printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
-
- DUMP_UPD(old, new, PcdFspMrcDebugPrintErrorLevel);
- DUMP_UPD(old, new, PcdFspKtiDebugPrintErrorLevel);
- DUMP_UPD(old, new, PcdHsuartDevice);
-
- hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
-}
-
-/* Display the UPD parameters for SiliconInit */
-void soc_display_fsps_upd_params(
- const FSPS_UPD *fsps_old_upd,
- const FSPS_UPD *fsps_new_upd)
-{
- const FSP_S_CONFIG *new;
- const FSP_S_CONFIG *old;
-
- old = &fsps_old_upd->FspsConfig;
- new = &fsps_new_upd->FspsConfig;
-
- printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
-
- DUMP_UPD(old, new, PcdBifurcationPcie0);
- DUMP_UPD(old, new, PcdBifurcationPcie1);
- DUMP_UPD(old, new, PcdActiveCoreCount);
- DUMP_UPD(old, new, PcdCpuMicrocodePatchBase);
- DUMP_UPD(old, new, PcdCpuMicrocodePatchSize);
- DUMP_UPD(old, new, PcdEnablePcie0);
- DUMP_UPD(old, new, PcdEnablePcie1);
- DUMP_UPD(old, new, PcdEnableEmmc);
- DUMP_UPD(old, new, PcdEnableGbE);
- DUMP_UPD(old, new, PcdFiaMuxConfigRequestPtr);
- DUMP_UPD(old, new, PcdPcieRootPort0DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort1DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort2DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort3DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort4DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort5DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort6DeEmphasis);
- DUMP_UPD(old, new, PcdPcieRootPort7DeEmphasis);
- DUMP_UPD(old, new, PcdEMMCDLLConfigPtr);
-
- hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
-}
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index e2b47329..8376cf7 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -289,7 +289,7 @@
}
/* SPR has no per stack IOAPIC or CBDMA devices */
-#if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
+#if CONFIG(SOC_INTEL_COOPERLAKE_SP)
uint32_t enum_id;
// Add IOAPIC entry
enum_id = soc_get_iio_ioapicid(socket, stack);
@@ -322,7 +322,7 @@
dev = dev->sibling;
}
-#if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
+#if CONFIG(SOC_INTEL_COOPERLAKE_SP)
// Add VMD
if (hob->PlatformData.VMDStackEnable[socket][stack] &&
stack >= PSTACK0 && stack <= PSTACK2) {
@@ -606,10 +606,6 @@
dmar = (acpi_dmar_t *)current;
enum dmar_flags flags = DMAR_INTR_REMAP;
- /* SKX FSP doesn't support X2APIC, but CPX FSP does */
- if (CONFIG(SOC_INTEL_SKYLAKE_SP))
- flags |= DMAR_X2APIC_OPT_OUT;
-
printk(BIOS_DEBUG, "ACPI: * DMAR at %lx\n", current);
printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", flags);
acpi_create_dmar(dmar, flags, acpi_fill_dmar);
To view, visit change 80172. To unsubscribe, or for help writing mail filters, visit settings.