If you want to keep and fix the driver, I suggest to first
test at what stage (silicon init / notification phase?) FSP
configures things. coreboot's .final seems to run after the
PCI Enum Complete phase, but before the last two phases.

FSP does this in NotifyPhaseApi() - Begin [Phase: 00000020]
Coreboot does it in
Finalize devices...
PCI: 00:17.0 final

This is odd, if FSP runs first and should write a write-once
register, coreboot should not have any effect, right? Maybe
there is a bug in your FSP?

View Change

To view, visit change 41674. To unsubscribe, or for help writing mail filters, visit settings.