Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33033 )
Change subject: [WIP] ssdtgen for PNP devices ......................................................................
Patch Set 17:
Patch Set 17:
is this patch ready for review? the title still says [WIP], but the patch is marked as ready for review
It's both. I'm not sure if that's the way to go. 1) I though about patching sconfig to add ACPI HID identifiers to LDNs in the devicetree.cb, but we only care about "known" io ports, thus we can map "known" io ports to ACPI HID anywhere.
2) The current code places all LDNs under the parent, most times the PCI LPC bridge. I'd prefer to have all LDNs under a new "chip", the superio chip (that isn't a LDN). It would make the ACPI code generation easier, as it would never be disabled (as LDN0 can be), it would generate basic functions to access LDNs, acquire mutexes,...
3)to access the superio configuration it needs to know the port knocking sequence, but it's currently hardcoded and not stored in any LDN (struct device *).