Patrick Rudolph has uploaded this change for review.
[WIP]nehalem: Add x86_64 support
Use correct datasize to compile on x86_64.
Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
---
M src/arch/x86/Makefile.inc
M src/arch/x86/include/arch/cbfs.h
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/microcode/microcode_asm.S
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/x86/early_reset.S
M src/drivers/pc80/tpm/tis.c
M src/northbridge/intel/nehalem/raminit.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smihandler.c
14 files changed, 39 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/37371/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 45db303..a25d91a 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -126,7 +126,7 @@
$(eval $(call early_x86_stage,bootblock,elf64-x86-64))
endif
-bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
+bootblock-y += walkcbfs.S
else # ROMCC_BOOTBLOCK
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index ec367ed..78bf2ed 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -33,7 +33,7 @@
static void *walkcbfs(char *target)
{
struct cbfs_file *head = walkcbfs_head(target);
- if ((u32)head != 0)
+ if ((uintptr_t)head != 0)
return CBFS_SUBHEADER(head);
/* We should never reach this if 'target' exists */
@@ -51,7 +51,7 @@
static inline unsigned long findstage(char *target)
{
struct cbfs_stage_restricted *stage = walkcbfs(target);
- if ((u32)stage != 0)
+ if ((uintptr_t)stage != 0)
return stage->entry;
/* We should never reach this if 'target' exists */
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 5a668c4..e458302 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -220,8 +220,20 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
- subl $4, %esp
+ /* entry64.inc preserves ebx. */
+#include <cpu/x86/64bit/entry64.inc>
+
+#ifdef __x86_64__
+
+ movd %mm2, %rdi
+ shld %rdi, 32
+ movd %mm1, %rsi
+ or %rsi, %rdi /* tsc */
+
+ movd %mm0, %rsi /* BIST */
+#else
+ subl $4, %esp
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
@@ -229,6 +241,7 @@
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */
+#endif
before_c_entry:
post_code(0x29)
diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S
index 647f67c..b9c43cc 100644
--- a/src/cpu/intel/microcode/microcode_asm.S
+++ b/src/cpu/intel/microcode/microcode_asm.S
@@ -56,6 +56,7 @@
.section .text
.global update_bsp_microcode
+.code32
update_bsp_microcode:
/* Keep return address */
diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index a76a95d..d816b4e 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -3,12 +3,20 @@
if CPU_INTEL_MODEL_2065X
+config ARCH_EXP_X86_64
+ bool "Experimental 64bit support"
+ default n
+
config CPU_SPECIFIC_OPTIONS
def_bool y
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
+ select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64
+ select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64
+ select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64
+ select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64
select SMP
select SSE2
select UDELAY_TSC
diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S
index ec015abe..998ebda 100644
--- a/src/cpu/x86/early_reset.S
+++ b/src/cpu/x86/early_reset.S
@@ -21,6 +21,7 @@
.section .text
.global check_mtrr
+.code32
check_mtrr:
/* Use the MTRR default type MSR as a proxy for detecting INIT#.
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 39fa70d..27e11bd 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -55,7 +55,7 @@
/* the macro accepts the locality value, but only locality 0 is operational */
#define TIS_REG(LOCALITY, REG) \
- (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+ (void *)((uintptr_t)CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
/* hardware registers' offsets */
#define TIS_REG_ACCESS 0x0
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index a393cb7..673cb5a 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1999,7 +1999,7 @@
u32 offset;
u8 *base;
- base = (u8 *)(totalrank << 28);
+ base = (u8 *)(uintptr_t)(totalrank << 28);
for (offset = 0; offset < 9 * 480; offset += 2) {
write32(base + offset * 8, get_etalon2(flip, offset));
write32(base + offset * 8 + 4, get_etalon2(flip, offset));
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f13ced9..84960ea 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -482,7 +482,7 @@
struct me_hfs hfs;
u32 reg32;
- mei_base_address = (void *)
+ mei_base_address = (void *)(uintptr_t)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 5b38ea7..c0d2494 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -238,7 +238,7 @@
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+ printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_read_config32(dev, 0x120);
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2b48eab..6771a7a 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -598,7 +598,7 @@
/* Add it to SSDT. */
acpigen_write_scope("\\");
- acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_write_name_dword("NVSA", (uintptr_t) gnvs);
acpigen_pop_len();
}
}
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 63dff6a..62fd08a 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -372,7 +372,7 @@
struct me_hfs hfs;
u32 reg32;
- mei_base_address = (u32 *)
+ mei_base_address = (u32 *)(uintptr_t)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 2d9412a..33e717a 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -104,7 +104,7 @@
pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */
- abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+ abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 3668842..a68c89a 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -177,7 +177,7 @@
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (global_nvs_t *)(uintptr_t)((u32)state->rbx);
*smm_done = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
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