Patrick Rudolph has uploaded this change for review.

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cpu/intel/speedstep: Add comment to clarify define

Add a comment to clarify that the define must match the define in
southbridge headers.

Change-Id: Ie0e97b170c81e3bca38975d6a3fe9a368c70e622
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/include/cpu/intel/speedstep.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34360/1

diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 05d83ed..660e5ae 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -25,6 +25,7 @@
 
 /* MWAIT coordination I/O base address. This must match
  * the \_PR_.CP00 PM base address.
+ * PMB0_BASE - 0x10 should match PMBASE for legacy C-state emulation.
  */
 #define PMB0_BASE 0x510
 

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