[coreboot-gerrit] Change in coreboot[master]: nb/intel/x4x: Use postcar stage to tear down CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23495

Change subject: nb/intel/x4x: Use postcar stage to tear down CAR
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nb/intel/x4x: Use postcar stage to tear down CAR

This allows to cleanly migrate car globals

Change-Id: I5cebabe80da98744e33d29b22650d708c747ebde
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/Makefile.inc
M src/northbridge/intel/x4x/ram_calc.c
3 files changed, 8 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/23495/1

diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 9239637..5859398 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -28,6 +28,8 @@
    select RELOCATABLE_RAMSTAGE
    select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
    select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE

config CBFS_SIZE
    hex
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc
index 5c64ca7..92ed04a 100644
--- a/src/northbridge/intel/x4x/Makefile.inc
+++ b/src/northbridge/intel/x4x/Makefile.inc
@@ -27,4 +27,6 @@
 ramstage-y += gma.c
 ramstage-y += northbridge.c

+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 1009372..dd28951 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -103,8 +103,6 @@
    return (void *) top_of_ram;
 }

-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
 /* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 void *setup_stack_and_mtrrs(void)
@@ -112,7 +110,7 @@
    struct postcar_frame pcf;
    uintptr_t top_of_ram;

-	if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+	if (postcar_frame_init(&pcf, 1*KiB))
    	die("Unable to initialize postcar frame.\n");

/* Cache the ROM as WP just below 4GiB. */
@@ -131,8 +129,7 @@
    postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
    postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);

-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+	/* We don't return here */
+	return NULL;
 }